US2006055002A1PendingUtilityA1

Methods for enhancing die saw and packaging reliability

Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Sep 13, 2004Filed: Aug 3, 2005Published: Mar 16, 2006
Est. expirySep 13, 2024(expired)· nominal 20-yr term from priority
H10W 42/00H10W 10/17H10W 10/014H10P 54/00H10W 42/121B28D 5/0011
43
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Claims

Abstract

A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.

Claims

exact text as granted — not AI-modified
1 . A semiconductor wafer with die saw induced stress reduction mechanism having one or more circuits fabricated in at least one active area on a semiconductor substrate, and having a scribe line for cutting the active area there along, the wafer comprising: 
 at least one seal ring around the active area; and    at least one shallow trench isolation in the semiconductor substrate between the seal ring and the scribe line.    
   
   
       2 . The wafer of  claim 1 , wherein the seal ring is a continuous ring surrounding the active area.  
   
   
       3 . The wafer of  claim 1 , wherein the seal ring has a width more than about 10 μm.  
   
   
       4 . The wafer of  claim 1 , wherein the active area is a film stack containing one or more layers of conducting materials connected together through via contacts with dielectric materials implemented between the one or more layers.  
   
   
       5 . The wafer of  claim 1 , wherein the seal ring connects to ground via one or more contacts to the semiconductor substrate.  
   
   
       6 . The wafer of  claim 1 , wherein the shallow trench isolation is a trench filled with at least one dielectric material.  
   
   
       7 . The wafer of  claim 1  wherein the shallow isolation trench has a depth of at least 3000 Å.  
   
   
       8 . The wafer of  claim 1 , further comprising a ditch on the substrate between the seal ring and the scribe line.  
   
   
       9 . The wafer of  claim 8 , wherein the ditch is fabricated on top of the shallow trench isolation.  
   
   
       10 . A semiconductor wafer with die saw induced stress reduction mechanism having one or more circuits fabricated in at least one active area on a semiconductor substrate, and having a scribe line for cutting the active area there along, the wafer comprising: 
 at least one seal ring around the active area;    at least one shallow trench isolation in the semiconductor substrate between the seal ring and the scribe line; and    a ditch on the substrate between the seal ring and the scribe line and on top of the shallow trench isolation.    
   
   
       11 . The wafer of  claim 10 , wherein the seal ring has a width more than about 10 μm.  
   
   
       12 . The wafer of  claim 10 , wherein the seal ring connects to ground via one or more contacts to the semiconductor substrate.  
   
   
       13 . The wafer of  claim 10 , wherein the shallow trench isolation is a trench filled with at least one dielectric material.  
   
   
       14 . The wafer of  claim 10 , wherein the shallow isolation trench has a depth of at least 3000 Å.  
   
   
       15 . A method for reducing die saw induced stress on a circuit fabricated in an active area on a semiconductor substrate when the active area is cut along a scribe line, the method comprising: 
 fabricating a seal ring around the active area; and    fabricating a shallow trench isolation between the seal ring and the scribe line by etching into a portion of the semiconductor substrate.    
   
   
       16 . The method of  claim 15  further comprising fabricating a ditch on the semiconductor substrate between the seal ring and the scribe line on top of the shallow trench isolation.  
   
   
       17 . The method of  claim 15 , wherein the seal ring has a width more than about 10 μm.  
   
   
       18 . The method of  claim 15 , wherein the seal ring connects to ground via one or more contacts to the semiconductor substrate.  
   
   
       19 . The method of  claim 15 , wherein the shallow isolation trench has a depth of at least 3000 Å.

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