Layered semiconductor wafer with low warp and bow, and process for producing it

Abstract

Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

1 . A semiconductor wafer with a diameter of at least 200 mm, comprising a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm.  
   
   
       2 . The semiconductor wafer of  claim 1 , wherein the carrier wafer has a BMD density in the range from 1·10 3 /cm 2  to 1·10 6 /cm 2 .  
   
   
       3 . A semiconductor wafer with a diameter of at least 200 mm, comprising a carrier wafer consisting of silicon, an electrically insulating layer and a semiconductor layer located thereon, wherein the semiconductor wafer has a warp of less than 30 μm and a bow of less than 10 μm, and wherein the carrier wafer has a BMD density in the range from 1·10 3 /cm 2  to 1·10 6 /cm 2 .  
   
   
       4 . The semiconductor wafer of  claim 1 , which has a warp of less than 20 μm.  
   
   
       5 . The semiconductor wafer of  claim 1 , which has a bow of less than 5 μm.  
   
   
       6 . The semiconductor wafer of  claim 1 , wherein the carrier wafer has a BMD density in the range from 1·10 3 /cm 2  to 1·10 5 /cm 2 .  
   
   
       7 . The semiconductor wafer of  claim 1 , wherein the carrier wafer has an interstitial oxygen concentration in the range from 3·10 17 /cm 3  to 8·10 17 /cm 3  and a nitrogen concentration in the range from 1·10 13 /cm 3  to 5·10 15 /cm 3 .  
   
   
       8 . The semiconductor wafer of  claim 7 , wherein the carrier wafer has an interstitial oxygen concentration in the range from 5·10 17 /cm 3  to 7·10 17 /cm 3 .  
   
   
       9 . The semiconductor wafer of  claim 7 , wherein the carrier wafer has a nitrogen concentration in the range from 5·10 14 /cm 3  to 5·10 15 /cm 3 .  
   
   
       10 . The semiconductor wafer of  claim 9 , wherein the carrier wafer has an interstitial oxygen concentration in the range from 3·10 17 /cm 3  to 5·10 17 /cm 3 .  
   
   
       11 . The semiconductor wafer of  claim 1 , wherein the BMD density throughout the volume of the carrier wafer deviates by no more than 50% from the mean BMD density throughout the entire volume of the carrier wafer.  
   
   
       12 . A process for producing a semiconductor wafer of  claim 1 , comprising providing a semiconductor wafer with a diameter of at least 200 mm, which comprises a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, and heat treating the semiconductor wafer, in which heat treating the semiconductor wafer is heated at a heating rate of from 10 to 200° C./s to a temperature in the range from 1,100 to 1,250° C., is held in this temperature range for a period of 5 s to 300 s, and is then cooled at a cooling rate of from 0.5 to 25° C./s.  
   
   
       13 . The process of  claim 12 , in which the cooling rate is from 0.5 to 15° C./s.  
   
   
       14 . A process for producing a semiconductor wafer of  claim 1 , comprising providing a semiconductor wafer with a diameter of at least 200 mm, which comprises a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, and heat treating the semiconductor wafer, in which heat treating the semiconductor wafer is heated at a heating rate of from 10 to 200° C./s to a temperature in a first range from 1,100 to 1,250° C.; is held in the first temperature range for a first period of 5 s to 300 s; is then cooled at a first cooling rate of from 10 to 150° C./s until the temperature is in a second range of from 1,000 to 1,150° C., the temperature in the second range being lower than the temperature in the first range; is then held in the second temperature range for a second period of 10 s to 300 s;, and is then cooled at a second cooling rate of from 10 to 150° C./s.  
   
   
       15 . A process for producing a semiconductor wafer of  claim 1 , comprising providing a semiconductor wafer with a diameter of at least 200 mm, which comprises a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, and subjecting said semiconductor wafer to a first heat treatment, in which the semiconductor wafer is heated at a first heating rate of from 10 to 200° C./s to a temperature in a first range of from 1,100 to 1,250° C., is then held in the first temperature range for a first period of 5 s to 300 s, and is then cooled at a first cooling rate of from 10 to 150° C./s, and a second heat treatment of the semiconductor wafer, in which the semiconductor wafer is heated at a second heating rate of from 10 to 200° C./s until the temperature has reached a value in a second range of from 1,000 to 1,150° C., is then held in the second temperature range for a second period of 10 s to 300 s, and is then cooled at a second cooling rate of from 10 to 150° C./s.  
   
   
       16 . The process of  claim 14 , wherein the duration of the second period is from 30 s to 120 s.  
   
   
       17 . The process of  claim 15 , wherein the duration of the second period is from 30 s to 120 s.  
   
   
       18 . A process for producing a semiconductor wafer of  claim 1 , comprising providing of a semiconductor wafer with a diameter of at least 200 mm, which comprises a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, and subjecting said semiconductor wafer to a heat treatment in an atmosphere which contains more than 12,000 ppm of oxygen, in which the semiconductor wafer is heated at a heating rate of from 10 to 200° C. until the temperature has reached a value in the range from 1,100 to 1,250° C., is then held in this temperature range for a period of 5 s to 300 s, and is then cooled at a cooling rate of from 10 to 150° C./s.  
   
   
       19 . The process as claimed in  claim 18 , wherein the atmosphere contains at least 20,000 ppm of oxygen.  
   
   
       20 . A layered semiconductor wafer having a diameter of at least 200 mm, comprising a silicon carrier wafer, a semiconductor layer, and an electrically insulating layer therebetween, wherein said semiconductor wafer is layered as a result of a layer transfer process and is heat treated by minimally one RTA thermal treatment, said wafer having an interstitial oxygen content of from 3·10 17 /cm 3  to 8·10 17 /cm 3 , a BMD density in the range of 1·10 3 /cm 2  to 1·10 6 /cm 2 , said BMDs being uniformly distributed throughout the depth of the silicon carrier wafer, said semiconductor wafer having a warp of less than 30 μm, a bow of less than 10 μm, a DeltaWarp of less than 30 μm, and a DeltaBow of less than 10 μm.