Stacked packages

Abstract

A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

1 . A method of making semiconductor chip assembly comprising the steps of: 
 (a) stacking a plurality of units each including at least one semiconductor chip having at least one chip select contact and a plurality of other contacts and a circuit panel having a plurality of chip select terminals, a plurality of other terminals, and traces extending on or in the panel connected to said terminals, said traces of each panel including a plurality of traces connecting said other contacts with said other terminals, at least one trace of each said panel being a multi-branched trace associated with plurality of said chip select terminals on such panel, each such multi-branched trace including a common section and a plurality of branches, each one of the plurality of branches being associated with one said chip select terminals, each one of said branches defining a gap intervening between the common section of the trace incorporating such branch and the terminal associated with such branch;    (b) selectively connecting a bridging conductive element across the gap defined by at least one branch, but less than all branches, of each such multi-branched trace, whereby the common section of each multi-branched trace is connected to less than all of the chip select terminals associated with the branches of such multi-branched trace; and    (c) interconnecting terminals of different units to one another to form vertical buses, said selectively connecting and interconnecting steps being performed so that the chip select contacts of chips in different units are connected to different ones of said vertical buses.    
     
     
         2 . A method as claimed in  claim 1  wherein said circuit panels, prior to said selectively connecting step, are identical to one another.  
     
     
         3 . A method as claimed in  claim 2  further comprising the step of handling and stocking said units as mutually interchangeable parts prior to said selectively connecting step.  
     
     
         4 . A method as claimed in  claim 2  wherein said stacking step includes aligning corresponding terminals of circuit panels in different units with one another.  
     
     
         5 . A method as claimed in  claim 1  wherein said selectively connecting step is performed so that the common section of each said multi-branched trace is connected to only one select terminal of the circuit panel bearing such trace.  
     
     
         6 . A method as claimed in  claim 1  further comprising the step of forming said units by connecting chips to circuit panels, wherein said selectively connecting step is performed after said step of forming said units.  
     
     
         7 . A method as claimed in  claim 1  wherein said selectively connecting step is performed in the same facility as said stacking step.  
     
     
         8 . A method as claimed in  claim 1  wherein selectively connecting step includes applying wire bonds across at least some of said gaps.  
     
     
         9 . A method as claimed in  claim 11  wherein said selectively connecting step includes engaging a mass of material formed integrally with a wire between a tool and pads defining the gap and applying energy to the mass and pads while squeezing the mass between said tool and said pads, and then disconnecting the mass from the wire so as to leave said mass connected to the pads and bridging the gap.  
     
     
         10 . A method as claimed in  claim 1  wherein said selectively connecting step includes forming masses of an electrically conductive bonding material across at least some of said gaps.  
     
     
         11 . A method as claimed in  claim 10 , wherein said selectively connecting step includes the step of forming solder bridges across the at least some of said gaps.  
     
     
         12 . A method as claimed in  claim 11 , wherein said interconnecting step includes connecting bus solder masses between terminals of adjacent units, and wherein said step of forming said solder bridges includes forming said solder bridges integral with said bus solder masses.  
     
     
         13 . A method as claimed in  claim 12  wherein said branched traces define pads adjacent said select terminals but not connected thereto, and said step of forming said solder bridges integral with said solder masses includes applying auxiliary solder masses only on the pads of branches where said bridging conductive elements are to be formed so that said auxiliary solder masses merge with said bus solder masses.  
     
     
         14 . A method as claimed in  claim 12  wherein said branched traces define pads adjacent said select terminals but not connected thereto, and said step of forming said solder bridges integral with said solder masses includes selectively treating said circuit panels adjacent said pads and select terminals so that said bus solder masses flow to only the pads of branches where said bridging conductive elements are to be formed.  
     
     
         15 . A method as claimed in  claim 11 , wherein said steps of selectively connecting and interconnecting are performed during a common reflow process.  
     
     
         16 . A method as claimed in  claim 1 , wherein said steps of selectively connecting and interconnecting are performed at substantially the same time.  
     
     
         17 . A method of making connections between conductive elements on a circuit panel comprising the steps: 
 (a) squeezing a mass of an electrically conductive material between a tool and a pair of electrically conductive elements exposed at a top surface of the circuit panel and defining a gap therebetween while applying sonic energy to said mass so as to bond said mass to both of said conductive elements; and then    (b) retracting said tool so as to leave said mass bridging the gap between said conductive elements.    
     
     
         18 . A method as claimed in  claim 17  wherein said mass is formed integrally with a wire, the method further comprising severing the wire from the mass after said squeezing step.  
     
     
         19 . A method as claimed in  claim 18  wherein said mass is a ball having a diameter and said gap has a width less than the diameter of the ball.  
     
     
         20 . A method as claimed in  claim 19  wherein said gap has a width of 40 μm or less.  
     
     
         21 . A method as claimed in  claim 18  wherein said mass and said wire include material selected from the group consisting of gold, gold alloys, aluminum and aluminum alloys.  
     
     
         22 . A method as claimed in  claim 18  wherein said conductive elements are pads formed integrally with trace portions, whereby said mass connects said trace portions to form a continuous trace.  
     
     
         23 . A method as claimed in  claim 17  wherein said squeezing step includes supporting a bottom surface of said circuit panel opposite from said top surface on a support.