ESD protection circuit with low parasitic capacitance

Abstract

An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

1 . An electrostatic discharge (ESD) protection circuit comprising: 
 a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event; and    at least one MOS transistor, having a source shared with the silicon controlled rectifier, coupled between the circuit pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event,    wherein the silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the circuit pad and the shared source of the MOS transistor, for functioning as a bipolar transistor,    wherein in a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.    
     
     
         2 . The ESD protection circuit of  claim 1  wherein the second areas have substantially identical dimensions.  
     
     
         3 . The ESD protection circuit of  claim 2  wherein each of the second areas have a width ranging from 2 to 480 μm.  
     
     
         4 . The ESD protection circuit of  claim 1  wherein each of the second areas includes a plurality of transistors that jointly function as the MOS transistor.  
     
     
         5 . The ESD protection circuit of  claim 1  wherein the first diode is composed of a P-type doped region and an N well, in which the P-type doped region is disposed.  
     
     
         6 . The ESD protection circuit of  claim 5  wherein the second diode is composed of the N well and a P-type substrate, in which the N well is disposed.  
     
     
         7 . The ESD protection circuit of  claim 1  further comprising a third diode, coupled between the circuit pad and ground, wherein the layout view of the ESD protection circuit has a third area disposed at a longitudinal end of the first area for placement of the third diode.  
     
     
         8 . The ESD protection circuit of  claim 1  further comprising a first guard ring connected to a positive voltage and a second guard ring connected to ground, surrounding the first area and the second areas.  
     
     
         9 . An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit, the IC comprising: 
 a silicon controlled rectifier (SCR) diode area for placement of a first diode and a second diode, which are serially connected with one another in an opposite direction, for serving as a bipolar transistor that, in part, constructs the SCR; and    at least two sets of MOS transistor areas, having a plurality of transistors jointly functioning as the MOS transistor, disposed proximately at two sides of the SCR diode area, wherein a parasitic capacitance of the ESD protection circuit is determined by a number or size of the MOS transistor areas.    
     
     
         10 . The IC of  claim 9  wherein the MOS transistor areas have substantially identical dimensions.  
     
     
         11 . The IC of  claim 10  wherein each of the MOS transistor areas has a width ranging from 2 to 480 μm.  
     
     
         12 . The IC of  claim 9  wherein the trigger voltage of the SCR decreases as a number of the MOS transistor areas decreases.  
     
     
         13 . The IC of  claim 9  further comprising at least one additional diode area disposed at a longitudinal end of the SCR diode area.  
     
     
         14 . The IC of  claim 9  further comprising a first guard ring area connected to a positive voltage, surrounding the SCR diode area and the MOS transistor area.  
     
     
         15 . The IC of  claim 9  further comprising a second guard ring connected to ground, surrounding the SCR diode area and the MOS transistor areas.  
     
     
         16 . An integrated circuit (IC) layout for an electrostatic discharge (ESD) protection circuit having a silicon controlled rectifier (SCR) for bypassing an ESD current from a core circuitry during an ESD event, and a MOS transistor for reducing a trigger voltage of the silicon controlled rectifier during the ESD event, the IC layout comprising: 
 an SCR diode area for placement of a first diode and a second diode, which are serially connected with one another in an opposite direction, for serving as a bipolar transistor that, in part, constructs the SCR; and    at least two sets of MOS transistor areas, having a plurality of transistors jointly functioning as the MOS transistor, disposed proximately at two sides of the SCR diode area,    wherein the MOS transistor areas have substantially identical width ranging from 2 to 480 μm,    wherein a parasitic capacitance of the ESD protection circuit is adjusted by varying a number or size of the MOS transistor areas.    
     
     
         17 . The IC layout of  claim 16  wherein the trigger voltage of the SCR decreases as a number of the MOS transistor areas decreases.  
     
     
         18 . The IC layout of  claim 16  further comprising at least one additional diode area disposed at a longitudinal end of the SCR diode area.  
     
     
         19 . The IC layout of  claim 16  further comprising a first guard ring area connected to a positive voltage, surrounding the SCR diode area and the MOS transistor area.  
     
     
         20 . The IC layout of  claim 16  further comprising a second guard ring connected to ground, surrounding the SCR diode area and the MOS transistor areas.