Novel ESD protection scheme for core devices

Abstract

A circuit and a method for solving the general problem of protecting core devices in integrated circuits from electrostatic discharge damage is provided. This circuit and a method prevents ESD voltage breakdown of thin oxide field effect transistors which are directly connected to the core Vdd power supply. The embodiments of this invention use inverter buffers using a thick or thin oxide devices at the input to the core circuitry is to be protected. Other embodiments of this invention use pass transistor or transfer gates made with thick or thin oxide devices at the input to the core circuitry is to be protected.

1 . An electrostatic discharge circuit for protecting core devices in integrated circuit chips comprising: 
 an inverter buffer using a device having an oxide thicker than devices to be protected.    
   
   
       2 . The ESD circuit for protecting core devices in integrated circuit chip of  claim 1  wherein said inverter buffer using a device having an oxide thicker than devices to be protected comprises a p-channel metal oxide semiconductor field effect transistor, PMOS FET device connected to a core power supply voltage.  
   
   
       3 . The ESD circuit for protecting core devices in integrated circuit chip of  claim 2  wherein said thick oxide inverter buffer contains an NMOS FET device connected to said PMOS FET device.  
   
   
       4 . The ESD circuit for protecting core devices in integrated circuit chip of  claim 3  wherein said PMOS FET device has its source connected to said core power supply voltage, its drain connected to a drain of said NMOS FET device and to an input of circuitry to be protected, and its gate connected to ground and to the gate of said NMOS FET device.  
   
   
       5 . The ESD circuit for protecting core devices in integrated circuit chip of  claim 4  wherein said NMOS FET device has its drain connected to said source of said PMOS FET device, and to said input of circuitry to be protected, its source is connected to ground and its gate is connected to ground and to said gate of said PMOS FET device.  
   
   
       6 . An ESD circuit for protecting core devices in integrated circuit chips comprising: 
 a pass or transfer gate using a PMOS device having an oxide thicker than devices to be protected from ESD.    
   
   
       7 . The ESD circuit for protecting core devices in integrated circuit chips of  claim 6  wherein said transfer gate using a PMOS device having an oxide thicker than devices to be protected from ESD contains said PMOS device which is connected between a core power supply voltage and an input of said circuitry to be protected from ESD.  
   
   
       8 . The ESD circuit for protecting core devices in integrated circuit chips of  claim 7  wherein said said transfer gate using a PMOS device having an oxide thicker than devices to be protected from ESD has its source connected to said core power supply voltage, its gate connected to ground and its drain connected to said input of said circuitry to be protected, from ESD.  
   
   
       9 . An ESD circuit for protecting core devices in integrated circuit chips comprising: 
 a resistor at the input to the core circuitry to be protected from ESD.    
   
   
       10 . The ESD circuit for protecting core devices in integrated circuit chips of  claim 9  wherein said resistor is connected between a core power supply voltage and said input to the core circuitry to be protected from ESD.  
   
   
       11 . A method of protecting core devices in integrated circuits from electrostatic discharge, ESD, comprising the steps of: 
 providing an inverter buffer using a device having an oxide thicker than devices to be protected,    
   
   
       12 . The method of protecting core devices in integrated circuits from electrostatic discharge, ESD of  claim 11  wherein said inverter buffer using a device having an oxide thicker than devices to be protected contains a p-channel metal oxide semiconductor field effect transistor, PMOS FET device connected to a core power supply voltage.  
   
   
       13 . The method of protecting core devices in integrated circuits from electrostatic discharge, ESD of  claim 12  wherein said inverter buffer using a device having an oxide thicker than devices to be protected contains an NMOS FET device connected to said PMOS FET device.  
   
   
       14 . The method of protecting core devices in integrated circuits from electrostatic discharge, ESD of  claim 13  wherein said PMOS FET device has its source connected to said core power supply voltage, its drain connected to a drain of said NMOS FET device and to an input of circuitry to be protected, and its gate connected to ground and to the gate of said NMOS FET device.  
   
   
       15 . The method of protecting core devices in integrated circuits from electrostatic discharge, ESD of  claim 14  wherein said NMOS FET device has its drain connected to said source of said PMOS FET device, and to said input of circuitry to be protected, its source is connected to ground and its gate is connected to ground and to said gate of said PMOS FET device.  
   
   
       16 . A method of protecting core devices in integrated circuits from electrostatic discharge, ESD, comprising the steps of: 
 providing a resistor at an input to core circuitry to be protected from ESD.    
   
   
       17 . The method of protecting core devices in integrated circuits from electrostatic discharge, ESD of  claim 16  wherein said resistor is connected between a core power supply voltage and said input to core circuitry to be protected from ESD.