US2005233580A1PendingUtilityA1

Alignment pattern for a semiconductor device manufacturing process

Assignee: NEC ELECTRONICS CORPPriority: Nov 30, 2001Filed: Jun 15, 2005Published: Oct 20, 2005
Est. expiryNov 30, 2021(expired)· nominal 20-yr term from priority
Inventors:Chieri Teramoto
H10W 46/501H10W 46/00H10W 20/40H10D 64/011
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Claims

Abstract

An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat surface being lower in level than the top surface of the inter-layer insulator. The metal plug is buried within an alignment hole which completely penetrates the insulation layer and at least reaches the field oxide film, so that the alignment hole has a bottom level which is deeper than a bottom level of the inter-layer insulator.

Claims

exact text as granted — not AI-modified
1 . A method of forming an alignment pattern comprising the steps of: 
 selectively forming a field oxide film over a substrate;    forming an inter-layer insulator over a surface of said substrate and said field oxide film;    forming an alignment hole which completely penetrates said insulation layer and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator; and    forming a metal plug buried within said alignment hole, said metal plug having a flat surface lower in level than a top surface of said inter-layer insulator and sloped surfaces serving as an alignment pattern which communicate between said top surface of said inter-layer insulator and said flat surface of said metal plug.    
   
   
       2 . The method as claimed in  claim 1 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.  
   
   
       3 . The method as claimed in  claim 1 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said at least sloped surface is obtained by a chemical mechanical polishing process for said metal plug.  
   
   
       4 . The method as claimed in  claim 1 , wherein said at least sloped surface has a level-difference of not less than 200 nanometers.  
   
   
       5 . The method as claimed in  claim 1 , wherein said field oxide film is formed by a local oxidation of silicon method.  
   
   
       6 . The method as claimed in  claim 1 , wherein said field oxide film is formed by a recessed local oxidation of silicon method, so that said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.  
   
   
       7 . The method as claimed in  claim 1 , wherein said field oxide film is formed by a recessed local oxidation of silicon method, so that a majority part of said field oxide film is buried within said substrate.  
   
   
       8 . The method as claimed in  claim 1 , wherein said field oxide film is formed in a trench groove of said substrate so that at least a most part of said field oxide film is buried within said substrate.  
   
   
       9 . A method of forming an alignment pattern comprising the steps of: 
 selectively forming a field oxide film over a substrate;    forming an inter-layer insulator over a surface of said substrate and said field oxide film;    forming an alignment hole which completely penetrates said insulation layer and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator; and    forming an interconnection layer both over said top surface of said inter-layer insulator and within said alignment hole, and said interconnection layer having sloped surfaces serving as an alignment pattern positioned over a periphery of said alignment hole.    
   
   
       10 . The method as claimed in  claim 9 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.  
   
   
       11 . The method as claimed in  claim 9 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said interconnection layer is re-flown.  
   
   
       12 . The method as claimed in  claim 9 , wherein said field oxide film is formed by a local oxidation of silicon method.  
   
   
       13 . The method as claimed in  claim 9 , wherein said field oxide film is formed by a recessed local oxidation of silicon method, so that said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.  
   
   
       14 . The method as claimed in  claim 9 , wherein said field oxide film is formed by a recessed local oxidation of silicon method, so that a majority part of said field oxide film is buried within said substrate.  
   
   
       15 . The method as claimed in  claim 9 , wherein said field oxide film is formed in a trench groove of said substrate so that at least a most part of said field oxide film is buried within said substrate.

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