Inventor · disambiguated record
Chieri Teramoto
Also filed as: TERAMOTO CHIERI
1 granted patent·2 pending applications·7 citations·filing 2002–2008
31Inventor score
Technology areasH10W
Files withNEC ELECTRONICS CORP3
Top patents by PatentIndex Score
3 records- 0144US6917115B2Alignment pattern for a semiconductor device manufacturing processNEC ELECTRONICS CORP·Filed 2002·Granted Jul 12, 2005·7 cites·28 claims
- 0231US2005233580A1Alignment pattern for a semiconductor device manufacturing processNEC ELECTRONICS CORP·Filed 2005·Application pending·0 cites
- 0331US2008290523A1Semiconductor device including barrier metal and coating film and method for manufacturing sameNEC ELECTRONICS CORP·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →