Flash EEPROM with function bit by bit erasing

Abstract

A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line and also be programmed with enhanced bit alterability.

1 - 13 . (canceled)  
   
   
       14 . A method of forming a multi-bit flash cell comprising the steps of: 
 providing a substrate;    forming a first dielectric layer over said substrate;    forming a first polysilicon layer over said first dielectric layer;    forming a plurality of floating gates comprising said first polysilicon layer, wherein said plurality of floating gates are spaced apart by a plurality of openings over said first dielectric layer;    forming a second dielectric layer over said plurality of floating gates, including said plurality of openings;    forming a second polysilicon layer over said second dielectric layer;    forming a plurality of control gates comprising said second polysilicon layer over said second dielectric layer over said plurality of floating gates;    forming a third dielectric layer over said plurality of control gates;    forming a fourth dielectric layer over the inside walls of said plurality of openings;    forming a third polysilicon layer over first of said plurality of openings to form a first bit line over said substrate, and over last of said plurality of openings to form a second bit line over said substrate;    forming a fifth dielectric layer over said first bit line and over said second bit line; and    forming a fourth polysilicon layer over said fifth dielectric layer, including over said plurality of openings, to form a word line contacting select gates on said semiconductor substrate.    
   
   
       15 . The method according to  claim 14 , wherein said substrate is silicon having active and passive regions.  
   
   
       16 . The method according to  claim 14 , wherein said first dielectric layer is a floating gate oxide having a thickness between about 160 to 180 Å.  
   
   
       17 . The method according to  claim 14 , wherein said first polysilicon layer has a thickness between about 700 to 900 Å.  
   
   
       18 . The method according to  claim 14 , wherein said second dielectric layer is inter-gate oxide having a thickness between about 70 to 80 Å.  
   
   
       19 . The method according to  claim 14 , wherein said second polysilicon layer has a thickness between about 900 to 1100 Å.  
   
   
       20 . The method according to  claim 14 , wherein said third dielectric layer is silicon nitride having a thickness between about 1400 to 1600 Å.  
   
   
       21 . The method according to  claim 14 , wherein said fourth dielectric layer is an oxide spacer comprising a high temperature oxide having a thickness between about 400 to 600 Å.  
   
   
       22 . The method according to  claim 14 , wherein said third polysilicon layer has a thickness between about 1400 to 1600 Å.  
   
   
       23 . The method according to  claim 14 , wherein said fifth dielectric layer is select gate oxide having a thickness between about 150-250 Å.  
   
   
       24 . The method according to  claim 14 , wherein said fourth polysilicon layer has a thickness between about 1400 to 1600 Å.  
   
   
       25 . A programming method comprising the steps of: 
 providing a multi-bit split-gate {MSG) flash cell having a pair of source/drain (S/D) bit lines and N′=(1+N) stacked gates comprising floating gates (FGs) and control gates (CGs) spaced apart With N select gates (SGs) between said bit lines, where N equals any integer;    exchanging the address of control gates with those of transfer gates (TGs);    performing program (write) operation bit by bit, wherein programmed bit is selected by word line, bit line and control gate;    performing erase operation, wherein the erased bits are selected by word line, bit line and control gate and where the erasing can be bit by bit; and    performing read operation.    
   
   
       26 . The programming method according to  claim 25 , wherein said exchanging the address of CGs with those of TGs is accomplished for CGs of said stacked gates after the first stacked gate.  
   
   
       27 . The programming method according to  claim 26 , wherein said CG of said first stacked gate is impressed with a voltage higher than for said TGs to provide sufficient vertical electric field for programming.  
   
   
       28 . The programming method according to  claim 25 , wherein said TGs between said pair of S/D bit lines are used to turn on the substrate channel below un-selected bits through lower voltage impressed on the TGs.  
   
   
       29 . The programming method according to  claim 25 , wherein said SGs are also used to turn on the substrate channel below SGs during programming.  
   
   
       30 . The programming method according to  claim 25 , wherein said erase operation is page erase operation where erased bits are selected only by word line.  
   
   
       31 . The programming method according to  claim 25 , wherein said programming, erasing and reading an FG transistor is accomplished according to the following table:  
     
       
         
               
               
               
               
               
               
             
                   
                   
               
                   
                   
               
                   
                 Voltage 
                 Write 
                 Erase (1)   
                 Erase (2)   
                 Read 
               
                   
                   
               
                   
               
               
               
               
               
               
               
             
                   
                 V BL1   
                 5.5 
                  0 
                  0 
                 1.5 
               
                   
                 V CG   
                 10 
                  0 
                 6u/0s (3)   
                 1.5 
               
                   
                 V SG   
                 2 
                 13 
                 13 
                 2 
               
                   
                 V TG   
                 6 
                 — 
                 — 
                 6 
               
                   
                 V BL2   
                 0.5 
                  0 
                  0 
                 0 
               
                   
                   
               
                   
                     (1) Page erase    
               
                   
                     (2) Page or bit by bit erase    
               
                   
                     (3) 6 V for unselected cell(u), and 0 V for selected (s) cell.    
               
                   
                   
               
           
              
              
              
              
             
             
              
             
          
           
              
              
              
              
              
              
              
              
              
              
             
          
         
       
     
   
   
       32 - 34 . (canceled)