Shared contact for high-density memory cell design

Abstract

A new method and structure is created for a multi-transistor SRAM device. Standard processing steps are followed for the creation of CMOS devices of providing a patterned layer of gate material, of performing LDD impurity implants, of creating gate spacers. After the creation of the gate spacers, a new step of photoresist patterning and exposure is added. The mask for this additional step is a modified butt-contact mask, comprising enlarging the conventional butt-contact opening by between about 0.005 μm and 0.2 μm, an effect that can also be achieved by photo over-expose. This modified butt-contact mask exposes a spacer that is adjacent to the butt-contact hole, this spacer is removed. S/D impurity implant is performed after which conventional processing steps are applied for completion of the multi-transistor SRAM device.

1 - 22 . (canceled)  
   
   
       23 . A butt contact opening for high-density memory cells, comprising: 
 a silicon semiconductor substrate;    at least one patterned and etched layer of gate material forming a gate electrode;    a first gate spacer over a first sidewall of the at least one patterned and etched layer of gate material, the first gate spacer being opposite to a second sidewall of the at least one patterned and etched layer of gate material;    LDD and S/D impurity implants self-aligned with the at least one patterned and etched layer of gate material, the S/D impurity implant underlying the LDD impurity implant, the LDD implant and the S/D implant underlying and surrounding a corner where the second sidewall of the etched layer of gate material interfaces with the active surface of the substrate over which a butt contact is provided;    a well implant underlying the butt contact opening;    a layer of etch stop material over the substrate, including the at least one patterned and etched layer of gate material;    a layer of dielectric over the layer of etch stop material;    a butt contact opening through the layer of dielectric and the layer of etch stop material, a conventional contact opening through the layer of dielectric, the butt contact opening comprising and laterally extending from the second sidewall of the at least one patterned and etched layer of gate material; and    the butt contact opening and the conventional contact opening having been filled with a conductive interconnect.    
   
   
       24 . The butt contact opening of  claim 23 , additionally comprising salicided contact surfaces.  
   
   
       25 . The butt contact opening of  claim 23 , the gate material preferably comprising polysilicon.  
   
   
       26 . The butt contact opening of  claim 23 , the gate spacers preferably comprising silicon nitride.  
   
   
       27 . The butt contact opening of  claim 23 , the enlarged sizing rule comprising a pattern of an enlarged butt contact opening.  
   
   
       28 . The butt contact opening of  claim 23 , the enlarged sizing rule comprising an increased a sizing rule, increased by between about 0.005 and 0.2 μm.  
   
   
       29 - 39 . (canceled)  
   
   
       40 . A semiconductor device, comprising: 
 a substrate with a butt contact thereon;    a layer of gate material with a first sidewall and a second sidewall on the substrate, the second sidewall adjacent to the butt contact;    a first spacer over a first sidewall;    a LDD impurity implant substantially aligned with the layer of gate material; and    a S/D impurity implant underlying and surrounding the LDD impurity implant, the S/D impurity implant and the LDD impurity implant underlying and surrounding a corner where the second sidewall interfaces with the butt contact.    
   
   
       41 . The semiconductor device of  claim 40 , further comprising a silicide layer on the top surface of the layer of gate material, the second sidewall, and the butt contact.  
   
   
       42 . The semiconductor device of  claim 41 , further comprising: 
 a layer of etch stop material over the substrate and the layer of gate material;    a layer of dielectric over the layer of etch stop material; and    a butt contact opening through the layer of etch stop material and the layer of dielectric to the silicide layer on the butt contact, the butt contact opening comprising and laterally extending from the silicide layer on the second sidewall.