Method to make minimal spacing between floating gates in split gate flash

Abstract

A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

1 .- 14 . (canceled)  
   
   
       15 . An integrated circuit device comprising: 
 a dielectric layer overlying a substrate;    a patterned conductor layer overlying said dielectric layer;    a patterned first masking layer overlying said conductor layer;    spacers on sidewalls of said patterned first masking layer and overlying said patterned conductor layer wherein external edges of said patterned conductor layer and said spacers are aligned.    
   
   
       16 . The device according to  claim 15  wherein said patterned conductor layer comprises a floating gate for a non-volatile memory cell.  
   
   
       17 . The device according to  claim 15  wherein said patterned conductor layer comprises polysilicon.  
   
   
       18 . The device according to  claim 15  wherein said patterned first masking layer comprises silicon nitride.  
   
   
       19 . The device according to  claim 15  wherein said spacers comprise silicon nitride.  
   
   
       20 . The device according to  claim 15  wherein said external edges of said patterned conductor layer overlie isolation structures in said substrate.