US2005133931A1PendingUtilityA1

SiOC properties and its uniformity in bulk for damascene applications

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Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Oct 23, 2003Filed: Feb 1, 2005Published: Jun 23, 2005
Est. expiryOct 23, 2023(expired)· nominal 20-yr term from priority
Inventors:Syun-Ming JangChung-Chi KoTien-I BaoLih-Ping LiAi-Sen Liu
H10P 14/6922H10P 14/6336H10P 14/6532H10P 14/6334H10P 14/662H10W 20/096H10W 20/084H10W 20/074H10W 20/071
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Claims

Abstract

A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.

Claims

exact text as granted — not AI-modified
1 . A dual damascene structure, comprising: 
 a substrate;    a first patterned dielectric material sub-layer over the substrate;    a patterned hardened sub-layer upon the first patterned dielectric material sub-layer; the patterned hardened sub-layer and the first patterned dielectric material sub-layer having a via opening therethrough exposing a portion of the substrate; and    a second patterned dielectric material sub-layer upon the patterned hardened sub-layer; the second patterned sub-layer having a trench opening therethrough over the via opening.    
   
   
       2 . The structure of  claim 1 , wherein the first and second patterned dielectric material sub-layers are each comprised of SiOC.  
   
   
       3 . The structure of  claim 1 , wherein the first and second patterned dielectric material sub-layers each have a dielectric constant of from about 2.3 to 2.6.  
   
   
       4 . The structure of  claim 1 , wherein the first and second patterned dielectric material sub-layers each have a dielectric constant of greater than about 2.8.  
   
   
       5 . The structure of  claim 1 , wherein the hardened layer has a thickness of from about 250 to 500 Å.  
   
   
       6 . The structure of  claim 1 , wherein the hardened layer has a thickness of from about 300 to 450 Å.  
   
   
       7 . The structure of  claim 1 , wherein the hardened layer is an etch stop layer.  
   
   
       8 . A dielectric material structure, comprising: 
 a substrate;    one or more dielectric material sub-layers over the substrate;    one or more respective hardened layers upon the one or more dielectric material sub-layers; and    an uppermost dielectric material sub-layer upon the uppermost one or more respective hardened layer.    
   
   
       9 . The structure of  claim 8 , wherein the one or more dielectric material sub-layers and the uppermost dielectric material sub-layer are each comprised of SiOC.  
   
   
       10 . The structure of  claim 8 , wherein the one or more dielectric material sub-layers and the uppermost dielectric material sub-layer each have a dielectric constant of from about 2.3 to 2.6.  
   
   
       11 . The structure of  claim 8 , wherein the one or more dielectric material sub-layers and the uppermost dielectric material sub-layer each have a dielectric constant of greater than about 2.8.  
   
   
       12 . The structure of  claim 8 , wherein the one or more respective hardened layers each have a thickness of from about 250 to 500 Å.  
   
   
       13 . The structure of  claim 8 , wherein the one or more respective hardened layers each have a thickness of from about 300 to 450 Å.  
   
   
       14 . The structure of  claim 8 , wherein the one or more respective hardened layers are etch stop layers.  
   
   
       15 . An apparatus comprising a substrate, and a low-k dielectric material layer formed over the substrate, the low-k dielectric material layer including: 
 a first dielectric material sub-layer disposed over the substrate, the first dielectric material sub-layer including a hardened layer at an upper surface thereof; and    a second dielectric material sub-layer disposed over the hardened layer.    
   
   
       16 . The apparatus of  claim 15 , wherein the first dielectric material sub-layer is made of SiOC.  
   
   
       17 . The apparatus of  claim 15 , wherein the first dielectric material sub-layer has a dielectric constant in the range of about 2.3 to 2.6.  
   
   
       18 . The apparatus of  claim 15 , wherein the hardened layer has a thickness in the range of about 250 to 500 Å.  
   
   
       19 . The apparatus of  claim 15 , wherein the hardened layer has a thickness in the range of about 300 to 450 Å.  
   
   
       20 . The apparatus of  claim 15 , wherein the hardened layer is made from a material that can function as an etch stop layer.  
   
   
       21 . The apparatus of  claim 15 , including: 
 a trench opening extending within the second dielectric material sub-layer above the hardened layer; and    a via opening extending through the hardened layer and the first dielectric material sub-layer from the trench opening to a portion of the substrate.

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