Extendable method for revising patterned microelectronic conductor layer layouts

Abstract

Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring location within which may be formed at least one optional wiring pattern. When there is designed within an unoccupied equivalent wiring location for a single wiring layout record within the series of wiring layout records at least one optional wiring pattern and an interconnect option to the at least one optional wiring pattern.

1 - 7 . (canceled)  
   
   
       8 . A method for generating a mapping table for revising a conductor layer layout comprising: 
 inputting a switch mapping file containing N+M records;    determining for each of the N+M records if a switch is in a first state or a second state; and    storing in a first file all records having a switch in a first state and storing in a second file all records having a switch in a second state.    
   
   
       9 . The method of  claim 8  wherein the first state is a connected state.  
   
   
       10 . The method of  claim 9  wherein the first file is an on file.  
   
   
       11 . The method of  claim 8  wherein the second state is an open state.  
   
   
       12 . The method of  claim 11  wherein the second file in an off file.  
   
   
       13 - 29 . (canceled)