Novel gate structure and method of forming the gate dielectric with mini-spacer

Abstract

A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

1 - 9 . (canceled)  
   
   
       10 . An FET gate structure comprising 
 high-k gate dielectric on a substrate,    gate conductor on said dielectric, and    high-k spacer surrounding said gate conductor and gate dielectric.    
   
   
       11 . An FET gate structure according to  claim 10 , wherein said gate dielectric is selected from the group comprising Zr x O y , Hf x O y , Ta x O y , Ti x O y , Al x O y , Hf x Si y O z , and Zr x Si y O z .  
   
   
       12 . A gate structure according to  claim 10 , wherein said gate conductor is selected from the group comprising silicon-based gate material and metal-based gate material.  
   
   
       13 . A gate structure according to  claim 12 , wherein said silicon-based gate material is selected from the group comprising single crystal silicon, poly silicon, doped silicon, doped poly-silicon, amorphous silicon, and silicon-germanium.  
   
   
       14 . A gate structure according to  claim 12 , wherein said metal-based gate material is selected from the group comprising tungsten, tungsten nitride, aluminum, Ti x N y , Ta x N y , copper, WSi x , and CoSi x .  
   
   
       15 . An FET device comprising 
 a silicon substrate;    source and drain regions on said silicon substrate;    transistor gate structure having a gate conductor and a high-k gate dielectric disposed between said gate conductor and said substrate; and    high-k spacers surrounding said gate conductor and high-k gate dielectric.    
   
   
       16 . An FET device according to  claim 15 , wherein the said gate dielectric film is selected from the group comprising Zr x O y , Hf x O y , Ta x O y , Ti x O y , Al x O y , Hf x Si y O z , and Zr x Si y O z .  
   
   
       17 . An FET device according to  claim 15 , wherein said gate conductor is selected from the group comprising silicon-based gate material and metal-based gate material.  
   
   
       18 . An FET device according to  claim 17 , wherein said silicon-based gate material is selected from the group comprising single crystal silicon, poly silicon, doped silicon, doped poly-silicon, amorphous silicon, and silicon-germanium.  
   
   
       19 . An FET device according to  claim 17 , wherein said metal-based gate material is selected from the group comprising tungsten, tungsten nitride, aluminium, Ti x N y , Ta x N y , copper, WSi x , and CoSi x .