US2005042859A1PendingUtilityA1

Etching process for high-k gate dielectrics

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Assignee: TAIWAN SEMICONDUCTOR MFGPriority: May 15, 2002Filed: Oct 8, 2004Published: Feb 24, 2005
Est. expiryMay 15, 2022(expired)· nominal 20-yr term from priority
Inventors:Mo YuYuan-Hung Chiu
H10P 76/2043H10P 50/73H10P 50/285H10D 64/691
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Claims

Abstract

A method of forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a patterned gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

Claims

exact text as granted — not AI-modified
1 . A method of forming a gate electrode, comprising the steps of: 
 providing a substrate having a high-k gate dielectric layer formed thereover;    forming a gate layer over the high-k gate dielectric layer;    forming a gate ARC layer over the gate layer;    patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;    partially etching the high-k gate dielectric layer not under the patterned gate layer using an F-based-chemistry plasma etch including an F-based-chemistry, and forming a smooth exposed upper surface of the patterned gate layer; and    then removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.    
   
   
       2 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of C x F y , C x H y F z  and S x F y .  
   
   
       3 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 , C 2 F 6 , C 4 F 6 , C 4 F 8 , CHF 3 , CH 2 F 2 , CH 3 F, SF 6 , CF 4 /Ar/O 2  and CF 4 /Ar.  
   
   
       4 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 /Ar/O 2  and CF4/Ar.  
   
   
       5 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.  
   
   
       6 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 1 to 100 sccm;    Ar: from about 10 to 1000 sccm;    top power: from about 100 to 1000 Watts;    bottom power: from about 0 to 500 Watts; and    pressure: from about 1 to 200 mTorr.    
   
   
       7 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 5 to 30 sccm;    Ar: from about 50 to 300 sccm;    top power: from about 300 to 700 Watts;    bottom power: from about 50 to 200 Watts; and    pressure: from about 2 to 50 mTorr.    
   
   
       8 . The method of  claim 1 , wherein the patterned gate ARC layer is removed from over the patterned gate layer by the Ar sputter or the F-based-chemistry plasma etch.  
   
   
       9 . The method of  claim 1 , wherein the patterned gate ARC layer is removed from over the patterned gate layer by the Ar sputter or the F-based-chemistry plasma etch and whereby the patterned gate ARC layer minimizes loss of the patterned gate layer during the Ar sputter or the F-based-chemistry plasma etch.  
   
   
       10 . The method of  claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter or an F based chemistry plasma and the partially etched high-k gate dielectric layer portions not under the patterned gate layer is etched using an H 2 SO 4  wet etch chemistry process.  
   
   
       11 . A method of forming a gate electrode, comprising the steps of: 
 providing a substrate having a high-k gate dielectric layer formed thereover;    forming a gate layer over the high-k gate dielectric layer;    forming a gate ARC layer over the gate layer;    patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;    removing the patterned ARC layer from over the patterned gate layer;    subjecting the structure to an Ar sputter or an F-based-chemistry plasma etch to partially etch the high-k gate dielectric layer not under the patterned gate layer using an F-based-chemistry plasma etch, and to form a smooth exposed upper surface of the patterned gate layer; and    removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer using an H2SO4 wet etch chemistry process to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.    
   
   
       12 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of C x F y , C x H y F z  and S x F y .  
   
   
       13 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 , C 2 F 6 , C 4 F 6 , C 4 F 8 , CHF 3 , CH 2 F 2 , CH 3 F, SF 6 , CF 4 /Ar/O 2  and CF 4 /Ar.  
   
   
       14 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 /Ar/O 2  and CF 4 /Ar.  
   
   
       15 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.  
   
   
       16 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 1 to 100 sccm;    Ar: from about 10 to 1000 sccm;    top power: from about 100 to 1000 Watts;    bottom power: from about 0 to 500 Watts; and    pressure: from about 1 to 200 mTorr.    
   
   
       17 . The method of  claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 5 to 30 sccm;    Ar: from about 50 to 300 sccm;    top power: from about 300 to 700 Watts;    bottom power: from about 50 to 200 Watts; and    pressure: from about 2 to 50 mTorr.    
   
   
       18 . A method of forming a gate electrode, comprising the steps of: 
 providing a substrate having a high-k gate dielectric layer formed thereover;    forming a gate layer over the high-k gate dielectric layer;    forming a gate ARC layer over the gate layer;    patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;    subjecting the structure to an Ar sputter or an F-based-chemistry plasma etch to partially etch the high-k gate dielectric layer not under the patterned gate layer and to remove the patterned ARC layer leaving a smooth exposed upper surface of the patterned gate layer; and    removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer using an H 2 SO 4  wet etch chemistry process to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.    
   
   
       19 . The method of  claim 18 , wherein the substrate is a silicon substrate; the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSO 4 , HfSO 4 , LaSO 4 , YSO 4 , ZrSi x O y  and HfSi x O y ; the gate layer is comprised of a material selected from the group consisting of polysilicon, polycide and a poly-Si/poly-Ge stack structure; and the gate ARC layer is comprised of a material selected from the group consisting of SiN, SiON, silicon oxide, organic ARC and an organic ARC/SiON stack structure.  
   
   
       20 . The method of  claim 18 , wherein the substrate is a silicon substrate; the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSi x O y  and HfSi x O y ; the gate layer is comprised of polysilicon; and the gate ARC layer is comprised of an organic ARC/SiON stack structure.  
   
   
       21 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters: 
 Ar: from about 20 to 500 sccm;    power: from about 200 to 2000 Watts;    temperature: from about 0 to 100° C.;    pressure: from about 5 to 50 mTorr; and    time: from about 5 to 30 seconds.    
   
   
       22 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters: 
 Ar: from about 100 to 200 sccm;    power: from about 300 to 500 Watts;    temperature: from about 80 to 90° C.;    pressure: from about 20 to 50 mTorr; and    time: from about 5 to 10 seconds.    
   
   
       23 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of C x F y , C x H y F z  and S x F y .  
   
   
       24 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 , C 2 F 6 , C 4 F 6 , C 4 F 8 , CHF 3 , CH 2 F 2 , CH 3 F, SF 6 , CF 4 /Ar/O 2  and CF 4 /Ar.  
   
   
       25 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF 4 /Ar/O 2  and CF 4 /Ar.  
   
   
       26 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.  
   
   
       27 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 1 to 100 sccm;    Ar: from about 10 to 1000 sccm;    top power: from about 100 to 1000 Watts;    bottom power: from about 0 to 500 Watts; and    pressure: from about 1 to 200 mTorr.    
   
   
       28 . The method of  claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters: 
 CF4: from about 5 to 30 sccm;    Ar: from about 50 to 300 sccm;    top power: from about 300 to 700 Watts;    bottom power: from about 50 to 200 Watts; and    pressure: from about 2 to 50 mTorr.    
   
   
       29 . The method of  claim 18 , wherein the H 2 SO 4  wet etch chemistry process is conducted at the following parameters: 
 H 2 SO 4 : from about 2 to 20% by volume;    temperature: from about 25 to 130° C.; and    time: from about 10 to 30 seconds.    
   
   
       30 . The method of  claim 18 , wherein the H 2 SO 4  wet etch chemistry process is conducted at the following parameters: 
 H 2 SO 4 : from about 2 to 5% by volume;    temperature: from about 25 to 50° C.; and    time: from about 10 to 20 seconds.    
   
   
       31 . The method of  claim 18 , wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween.  
   
   
       32 . The method of  claim 18 , wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween; and wherein the Ar sputter or the F-based-chemistry plasma etch also etches and removes the interfacial layer not under the patterned gate layer.  
   
   
       33 . The method of  claim 18 , wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer.  
   
   
       34 . The method of  claim 18 , wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer; and wherein the STIs are not substantially affected by the H 2 SO 4  wet etch chemistry process.  
   
   
       35 . The method of  claim 18 , wherein high-k gate dielectric layer has a thickness of from about 10 to 50 Å; the gate layer has a thickness of from about 400 to 3000 Å; and the gate ARC layer has a thickness of from about 100 to 500 Å.  
   
   
       36 . The method of  claim 18  wherein high-k gate dielectric layer has a thickness of from about 20 to 50 Å; the gate layer has a thickness of from about 1200 to 1800 Å; and the gate ARC layer has a thickness of from about 200 to 400 Å.  
   
   
       37 . The method of  claim 18 , wherein the patterned gate ARC layer minimizes loss of the patterned gate layer during the Ar sputter or the F-based-chemistry plasma etch.

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