Method of fabricating flash memory device using sidewall process

Abstract

A method of fabricating a flash memory device includes depositing and etching an insulating layer on a substrate having STI structures, depositing a first polysilicon layer over the insulating layer and the substrate, etching the first polysilicon layer to form floating gates and removing the insulating layer. The method also includes forming a first photoresist pattern, performing a first ion implantation using the first photoresist pattern to form first source/drain regions in the substrate and adjacent to the floating gate, removing the first photoresist pattern, depositing an ONO layer on the resulting structure, depositing a second polysilicon layer over the ONO layer, and etching the second polysilicon layer to form a control gate and at least one select gate. The method concludes by forming a second photoresist pattern and performing a second ion implantation using the second photoresist pattern to form second source/drain regions in the substrate and adjacent to the select gate.

1  A method for fabricating a flash memory device using a sidewall process comprising: 
 depositing and etching an insulating layer on a substrate having shallow trench isolation (STI) structures formed therein;    depositing a first polysilicon layer over the insulating layer and the substrate;    etching the first polysilicon layer to form floating gates;    removing the insulating layer;    forming a first photoresist pattern;    performing a first ion implantation using the first photoresist pattern to form first source/drain regions in the substrate and adjacent to the floating gate;    removing the first photoresist pattern;    depositing an oxide-nitride-oxide (ONO) layer on the resulting structure;    depositing a second polysilicon layer over the ONO layer;    etching the second polysilicon layer to form a control gate and at least one select gate;    forming a second photoresist pattern; and    performing a second ion implantation using the second photoresist pattern to form second source/drain regions in the substrate and adjacent to the select gate.    
   
   
       2 . The method as defined by  claim 1 , wherein the insulating layer has a thickness between 2000 Å and 3000 Å.  
   
   
       3 . The method as defined by  claim 1 , wherein the insulating layer is etched to form at least a trench therein, and the first polysilicon layer is etched to form polysilicon sidewalls serving as the floating gates on side surfaces of the trench.  
   
   
       4 . The method as defined by  claim 1 , wherein the first polysilicon layer has a thickness between 4000 Å and 6000 Å.  
   
   
       5 . The method as defined by  claim 1 , wherein the first polysilicon layer is etched without a mask pattern to form the floating gates.  
   
   
       6 . The method as defined by  claim 1 , wherein the insulating layer is removed by means of wet-etching after the formation of the floating gates.  
   
   
       7 . The method as defined by  claim 1 , wherein the first ion implantation is performed after the floating gates are formed.  
   
   
       8 . The method as defined by  claim 1 , wherein the ONO layer comprises a first oxide layer with a thickness between 50 Å and 100 Å, a nitride layer with a thickness between 50 Å and 100 Å, and a second oxide layer with a thickness between 300 Å and 400 Å.  
   
   
       9 . The method as defined by  claim 1 , wherein the second polysilicon layer has a thickness between 1500 Å and 2500 Å.  
   
   
       10 . The method as defined by  claim 1 , wherein the control gate and the select gate are simultaneously formed during the etching of the second polysilicon layer.  
   
   
       11 . A flash memory comprising the floating gate fabricated by the method of  claim 1.