Pre-etching plasma treatment to form dual damascene with improved profile
Abstract
A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer including a photoresist layer having a photolithographically patterned portion for etching a feature through a thickness portion of at least one underlying dielectric layer; and, plasma treating the photoresist layer with a carbon monoxide (CO) containing plasma to induce a polymeric cross-linking reaction at the photoresist layer surface to decrease a photoresist layer etching rate in a subsequent etching process; and, etching said feature through the thickness portion to maintain a width dimension of said feature including the photolithographically patterned portion within a pre-determined dimensional variation.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for plasma etching a semiconductor feature to improve an etching profile comprising the steps of:
providing a semiconductor wafer comprising a photoresist layer having a photolithographically patterned portion for etching a feature through a thickness portion of at least one underlying dielectric layer; and, plasma treating the photoresist layer with a carbon monoxide (CO) containing plasma to induce a polymeric cross-linking reaction at the photoresist layer surface to decrease a photoresist layer etching rate in a subsequent etching process; and, etching said feature through the thickness portion to maintain a width dimension of said feature including the photolithographically patterned portion within a pre-determined dimensional variation.
2 . The method of claim 1 , wherein the semiconductor wafer further comprises a first feature opening etched though a first thickness portion of at least one dielectric insulating layer.
3 . The method of claim 2 , wherein said feature is formed overlying an encompassing said first feature.
4 . (not entered)
5 . The method of claim 4 , wherein said feature is a trench opening and said first feature opening is a via opening comprising a dual damascene structure.
6 . The method of claim 5 , wherein the step of plasma treating further removes photoresist residue along a sidewall of said via opening above a resinous via plug filling a portion of said via opening.
7 . The method of claim 6 , wherein following the step of etching, said via opening is substantially free of an etching resistant etching residue protruding above a bottom portion of the trench opening.
8 . The method of claim 2 , wherein the at least one dielectric insulating layer comprises a member selected from the group consisting of organo silicate glass (OSG) and fluorinated silicate glass (FSG).
9 . The method of claim 1 , wherein said CO containing plasma is formed by a plasma source gas mixture comprising carbon monoxide and at least one diluent gas selected from the group consisting of helium, argon, nitrogen, and oxygen.
10 . The method of claim 1 , wherein carbon monoxide in said CO containing plasma chemically reacts with the photoresist layer to reduce an etching rate of the photoresist layer.
11 . The method of claim 9 , wherein said plasma source gas mixture comprises a volumetric percent ratio of carbon monoxide to diluent gas of about 30 to 70 volume percent to about 70 to 30 volume percent with respect to said plasma source gas mixture volume.
12 . The method of claim 1 , wherein the step of etching said feature is carried out in-situ following the step of plasma treating.
13 . A method for plasma etching a dual damascene structure to improve an etching profile and critical dimension etching bias comprising the steps of:
providing a semiconductor wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer and having a photolithographically patterned overlying photoresist layer for etching a trench opening overlying the via opening; plasma treating the photoresist layer with a carbon monoxide (CO) containing plasma to remove photoresist residue along a portion of the via opening sidewall; and, etching the trench opening in-situ overlying and at least partially encompassing the via opening according to a reactive ion etch (RIE) process to remain within a critical dimension (CD) etching bias window.
14 . The method of claim 13 wherein the step of plasma treating induces a polymeric cross-linking reaction at the photoresist layer surface to decrease a photoresist layer etching rate in the step of etching the trench opening to remain within a critical dimension (CD) etching bias window.
15 . The method of claim 13 , wherein the via opening comprises above a resinous via plug filling a portion of the via opening.
16 . The method of claim 13 , wherein following the step of etching, the via opening at the trench level is substantially free of an etching resistant etching residue.
17 . The method of claim 13 , wherein the at least one dielectric insulating layer comprises a member selected from the group consisting of organo silicate glass (OSG) and fluorinated silicate glass (FSG).
18 . The method of claim 1 , wherein the CO containing plasma is formed by a plasma source gas mixture comprising carbon monoxide and at least one diluent gas selected from the group consisting of helium, argon, nitrogen, and oxygen.
19 . The method of claim 18 , wherein the plasma source gas mixture comprises a volumetric percent ratio of carbon monoxide to diluent gas of about 30 to 70 volume percent to about 70 to 30 volume percent with respect to the plasma source gas mixture volume.
20 . The method of claim 1 , wherein the step of etching the trench opening is carried out in-situ following the step of plasma treating.Join the waitlist — get patent alerts
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