High performance chip scale leadframe package and method of manufacturing the package

Abstract

An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.

What is claimed is:  
     
         1 . An integrated circuit package comprising: 
 a) a plurality of leads each having a first face and a second face opposite to said first face;    b) a die pad having a first face and a second face opposite to said first face, wherein said second face of said die pad is orthogonally offset from said second face of said leads, such that said second face of said die pad and said second face of said leads are not coplanar;    c) an integrated circuit chip substantially laterally disposed between said plurality of leads and having a first face and a second face opposite to said first face, whereby said first face of said integrated circuit chip is proximate to said second face of said die pad and is coupled to said second face of said die pad; and    d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each of said plurality of wires comprising: 
 a first end electrically conductively joined to said first face of said IC chip, wherein said first end is disposed between a plane defined by said second face of said die pad and a plane defined by said first face of said integrated circuit chip, and  
 a second end electrically conductively joined to said first face of one of said plurality of leads, wherein said second end is disposed between a plane defined by said first face of said die pad and a plane defined by said first face of one of said plurality of leads.  
   
     
     
         2 . The integrated circuit package according to  claim 1 , wherein said first face of said die pad is adapted to direct coupling with a thermal dissipation element.  
     
     
         3 . The integrated circuit package according to  claim 1 , further comprising: 
 e) an encapsulant surrounding said first face of said integrated circuit chip, said first faces of said plurality of leads, said wires, and said second face of said die pad, and wherein said first face of said die pad is adapted to direct coupling with a thermal dissipation element.    
     
     
         4 . The integrated circuit package according to  claim 3 , wherein said encapsulant is a polymer-based molding compound.  
     
     
         5 . The integrated circuit package according to  claim 3 , wherein a planar surface is formed comprising said first face of said die pad and an outer surface of said encapsulant.  
     
     
         6 . The integrated circuit package according to  claim 1 , wherein said plurality of leads and said die pad are composed of a common copper alloy.  
     
     
         7 . The integrated circuit package according to  claim 1 , wherein said plurality of wires are composed of one of a group comprising: gold, gold with some level of impurities, aluminum, and copper.  
     
     
         8 . The integrated circuit package according to  claim 1 , further comprising: 
 e) a thermal dissipation element having a first face and a second face opposite to said first face, wherein said second face of said thermal dissipation element is coupled to said first face of said die pad    
     
     
         9 . The integrated circuit package according to  claim 8 , wherein said thermal dissipation element comprises a heat sink for a single integrated circuit chip  
     
     
         10 . The integrated circuit package according to  claim 8 , wherein said thermal dissipation element comprises a heat sink for a plurality of integrated circuit chips.  
     
     
         11 . The integrated circuit package according to  claim 1 , wherein: 
 said second face of said die pad comprises: 
 an inner surface,  
 a peripheral surface, and  
 an edge defining the boundary between said inner surface and said peripheral surface; and  
   wherein the space between said inner surface and said first face is greater than the space between said peripheral surface and said first face, such that said inner portion is offset from said peripheral portion.    
     
     
         12 . The integrated circuit according to  claim 1 , wherein said second face of said die pad comprises: 
 an inner surface,    a peripheral surface, and    a reservoir defining the boundary between said inner surface and said peripheral surface.    
     
     
         13 . the integrated circuit package according to  claim 1 , wherein: 
 said plurality of leads and said die pad are formed from a leadframe, said leadframe comprising: 
 an outer frame supporting said plurality of leads extending substantially inward from said outer frame, and  
 a plurality of tie bars securing said outer frame to said die pad, substantially centrally disposed within said outer frame; and  
   wherein each of said plurality of tie bars includes a mechanical depression, such that an offset is created between said die pad and said plurality of leads.    
     
     
         14 . An integrated circuit package comprising: 
 a) a plurality of leads each having a first face and a second face opposite to said first face;    b) a die pad having a first face and a second face opposite to said first face, wherein said second face of said die pad is orthogonally offset from said second face of said leads, such that said second face of said die pad and said second face of said leads are not coplanar;    c) an integrated circuit chip substantially laterally disposed between said plurality of leads and having a first face and a second face opposite to said first face, whereby said first face of said integrated circuit chip is proximate to said second face of said die pad and is coupled to said second face of said die pad;    d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each comprising: 
 a first end electrically conductively joined to said first face of said integrated circuit chip, and  
 a second end electrically conductively joined to said first face of one of said plurality of leads;  
   e) an annular element substantially laterally disposed between said integrated circuit chip and said plurality of leads such that said annular element substantially encircles said integrated circuit chip; and    f) at least one secondary wire liking said integrated circuit chip to said annular element, each having: 
 a first end electrically conductively joined to said first face of said integrated circuit chip, and  
 a second end electrically conductively joined to said first face of said annular element.  
   
     
     
         15 . The integrated circuit package according to  claim 14 , wherein said annular element is electrically grounded.  
     
     
         16 . The integrated circuit package according to  claim 14 , wherein said annular element comprises a power source.  
     
     
         17 . The integrated circuit package according to  claim 14 , wherein said annular element is circular.  
     
     
         18 . The integrated circuit package according to  claim 14 , wherein said annular element is elliptical.  
     
     
         19 . The integrated circuit package according to  claim 14 , wherein said annular element is a polygon.  
     
     
         20 . An integrated circuit package comprising: 
 a) a plurality of leads each having a first face and a second face opposite to said first face;    b) an integrated circuit chip substantially laterally disposed between said plurality of leads, and having a first face and a second face opposite to said first face;    c) a thermal dissipation element having a first face and a second face opposite to said first face, 
 wherein said second face of said thermal dissipation element is proximate to said first face of said integrated circuit chip and is coupled to said first face of said integrated circuit chip through a first coupling material, and  
 wherein said second face of said thermal dissipation element extends laterally such that it overhangs said first face of each of said plurality of leads; and  
   d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each comprising: 
 a first end electrically conductively joined to said first face of said integrated circuit chip, wherein said first end is disposed between said second face of said thermal dissipation element and said first face of said integrated circuit chip, and  
 a second end electrically conductively joined to said first face of one of said plurality of leads, wherein said second end is disposed between said second face of said thermal dissipation element and said first face of said one of said plurality of leads.  
   
     
     
         21 . The integrated circuit package according to  claim 20 , wherein said thermal dissipation element comprises a heat sink.  
     
     
         22 . The integrated circuit package according to  claim 20 , wherein said second face of said thermal dissipation element is further coupled to said first face of each of said plurality of leads through a second coupling material.  
     
     
         23 . The integrated circuit package according to  claim 22 , wherein said second coupling material is electrically non-conductive.  
     
     
         24 . The integrated circuit package according to  claim 22 , wherein said second coupling material is thermally conductive. 
 d) an annular element substantially laterally disposed between said integrated circuit chip and said plurality of leads, such that said annular element substantially encircles said integrated circuit chip; and    e) at least one secondary wire connecting said integrated circuit chip to said annular element, each of said at least one secondary wires comprising: 
 a first end electrically conductively joined to said first face of said integrated circuit chip, and  
 a second end electrically conductively joined to said first face of said annular element.