Scheme for eliminating the channel unexpected turn-on during ESD zapping

Abstract

This invention provides a circuit for eliminating unexpected transistor channel turn-on caused by electrostatic discharge, ESD, zapping. It provides circuits which detect ESD over-voltage conditions and which pull down the voltage to the sensitive logic devices in the input/output pre-driver circuitry during ESD zapping. There is an Input/Output control circuit which interfaces with the sense circuit, feedback circuit and with the input/output pad of the semiconductor chip to be protected from ESD damage. The purpose of this I/O circuit is to use the ESD sense circuit and an internal feedback node to pull down the voltage on the gates of the MOSFET devices most vulnerable to unexpected channel turn on during the during of the ESD over-voltage condition.

What is claimed is:  
     
         1 . A circuit for eliminating the channel unexpected turn-ON during electrostatic discharge, ESD, zapping, comprising: 
 an electrostatic discharge ESD sensing circuit, which interfaces with input/output, I/O circuitry, which is located at a chip I/O pad,    a feedback circuit, which interfaces with said ESD sensing circuit with an input/output, I/O, circuit, and    said input/output, I/O, circuit, which interfaces to an I/O pad and interfaces to said ESD sensing circuit.    
     
     
         2 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 1  wherein said ESD sensing circuit detects a high voltage caused by ESD at an internal sensing node.  
     
     
         3 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 1  wherein said sensing node detects a high voltage ESD event by being charged up via ‘n’ serially connected NMOS devices.  
     
     
         4 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 3  wherein said ‘n’ serial connected to NMOS devices are connected between the power supply node and said internal sensing node.  
     
     
         5 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 3  wherein said ‘n’ serially connected NMOS FETS have their drains and gates connected to the power supply voltage, and have their sources are connected to a gate and drain of a next serially connected NMOS FET.  
     
     
         6 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 5  wherein said second serially connected NMOS FET has its drain and gate connected to said source of said first serially connected NMOS FET and whose source is connected to the drain and gate of said nth serially connected NMOS FET.  
     
     
         7 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 3  wherein said nth serially connected NMOS FET has its drain and gate connected to said source of a last serially connected NMOS FET and whose source is connected to a second internal feedback node.  
     
     
         8 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 3  wherein said last serially connected NMOS FET has its drain and gate connected to said source of said previous serially connected NMOS FET, and whose source.  
     
     
         9 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains a discharge NMOS FET whose gate is connected to the source of said last serially connected NMOS FET device, whose drain is connected to an internal feedback node and whose source is connected to ground.  
     
     
         10 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains a second discharge NMOS FET whose gate is connected to the gate of a first PMOS FET source of said last serially connected NMOS FET device, whose drain is connected to an internal feedback node and whose source is connected to ground.  
     
     
         11 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains said first PMOS FET whose source is connected to said power supply, whose gate is connected to a gate of said second discharge NMOS FET, and whose drain is connected to a source of a second PMOS FET device.  
     
     
         12 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains said second PMOS FET whose source is connected to said drain of said first PMOS FET, whose gate is connected to said sensing node and whose drain is connected to said internal feedback node.  
     
     
         13 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains a resistor which is connected between the gate of said first discharge NMOS FET and ground.  
     
     
         14 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains said third PMOS FET whose source is connected to said power supply voltage, whose drain is connected to a drain of a third discharge NMOS FET and whose gate is connected to a drain of a fourth PMOS FET.  
     
     
         15 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 2  wherein said sensing circuit contains a said fourth PMOS FET whose drain is connected to a gate of said third PMOS FET, whose source is connected to said power supply voltage, and whose gate is connected to said drain of said third PMOS FET.  
     
     
         16 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 1  wherein said feedback circuit pulls down gate voltages of Input/output predriver devices to zero volts during an ESD zapping event.  
     
     
         17 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 16  where said feedback circuit contains a fourth PMOS FET whose source is connected to said power supply, whose drain is connected to the drain of a fourth NMOS FET, and whose gate is connected to the gate of a fifth discharge NMOS FET.  
     
     
         18 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 16  wherein said feedback circuit contains said fourth NMOS FET whose source is connected to the P side of a first PN diode and to the N-side of a second PN diode whose drain is connected to the drain of said fourth PMOS FET and whose gate is connected to the drain of said fifth discharge NMOS FET.  
     
     
         19 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 16  wherein said feedback circuit contains said fifth NMOS FET whose source is connected to ground; whose drain is connected to the drain of said fifth PMOS FET, and whose gate is connected to an output of a NOR gate.  
     
     
         20 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 16  wherein said feedback circuit contains a 2-input NOR whose first input is an output signal from a chip's logic core and whose second input is an output enable.  
     
     
         21 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 1  wherein said I/O circuit is used to discharge an ESD voltage to ground and is used to drive outputs off the chip.  
     
     
         22 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said I/O circuit contains a first IO PMOS FET whose source and gate are connected to Vcc and whose drain is connected to an I/O pad.  
     
     
         23 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said I/O circuit contains a first IO NMOS FET whose drain is connected to said drain of said first IO PMOS FET, whose gate and source are connected to ground.  
     
     
         24 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said I/O circuit contains a second IO PMOS FET whose source and gate are connected to said power supply voltage, and whose drain is connected to said I/O pad.  
     
     
         25 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains said second IO NMOS FET whose drain is connected to said drain of said second IO PMOS FET, and whose gate and source are connected to ground.  
     
     
         26 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains said third IO PMOS FET whose source is connected to said power supply voltage, whose gate is connected to a gate of a fourth IO PMOS FET, and whose drain is connected to said IO pad.  
     
     
         27 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains a fourth IO NMOS FET whose drain is connected to said IO pad, source is connected to ground, and whose gate is connected to said internal feedback node.  
     
     
         28 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains a third IO NMOS FET whose drain is connected to said drain of said third IO PMOS FET, whose gate is connected to said internal feedback node and whose source is connected to ground.  
     
     
         29 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains said fourth PMOS FET whose source is connected to said power supply voltage, whose gate is connected to said gate of said third IO PMOS FET, and whose drain is connected to the drain of said fourth IO NMOS FET.  
     
     
         30 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains a fifth IO NMOS FET whose drain is connected to one side of an IO resistor and whose gate and source are connected to ground.  
     
     
         31 . The circuit for eliminating the channel unexpected turn-ON during ESD zapping of  claim 21  wherein said IO circuit contains said IO resistor whose one side is connected to said drain of said fifth IO NMOS FET and whose other side is connected to said drain of said fourth IO NMOS FET.  
     
     
         32 . A method for eliminating the channel unexpected turn-ON during electrostatic discharge, ESD, zapping, comprising the steps of: 
 providing an electrostatic discharge ESD sensing circuit, which interfaces with input/output, I/O circuitry, which is located at a chip I/O pad,    providing a feedback circuit, which interfaces with said ESD sensing circuit and an input/output, I/O, circuit, and    providing said input/output, I/O, circuit, which interfaces to an I/O pad and interfaces to said ESD sensing circuit.    
     
     
         33 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 32  wherein said ESD sensing circuit detects a high voltage caused by ESD at an internal sensing node.  
     
     
         34 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 32  wherein said sensing node detects a high voltage ESD event by being charged up via ‘n’ serially connected NMOS devices.  
     
     
         35 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 34  wherein said ‘n’ serial connected to NMOS devices are connected between the power supply node and said internal sensing node.  
     
     
         36 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 34  wherein said ‘n’ serially connected NMOS FETS have their drains and gates connected to the power supply voltage, and have their sources are connected to a gate and drain of a next serially connected NMOS FET.  
     
     
         37 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 36  wherein said second serially connected NMOS FET has its drain and gate connected to said source of said first serially connected NMOS FET and whose source is connected to the drain and gate of said nth serially connected NMOS FET.  
     
     
         38 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 34  wherein said nth serially connected NMOS FET has its drain and gate connected to said source of a last serially connected NMOS FET and whose source is connected to an internal feedback node.  
     
     
         39 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 34  wherein said last serially connected NMOS FET has its drain and gate connected to said source of said previous serially connected NMOS FET, and whose source.  
     
     
         40 . The method for eliminating the channel unexpected turn-ON during ESD zapping of  claim 33  wherein said sensing circuit contains a discharge NMOS FET whose gate is connected to the source of said last serially connected NMOS FET device, whose drain is connected to said internal feedback node and whose source is connected to ground.