Method to improve the coupling ratio of top gate to floating gate in flash

Abstract

A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage. Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region. Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions. Top gates, comprised of conductive stripes that are perpendicular to the active regions, are disposed over floating gates from which they are separated by a top gate insulator layer.

What is claimed is:  
     
         1 . A structure to improve the coupling ratio of top gate to floating gate in flash memory cells, comprising: 
 parallel active regions, surrounded by isolation regions, over a semiconductor region of a substrate, said isolation regions having a portion within and a portion above said semiconductor region, and where the semiconductor region under said active region is doped in the vicinity of the surface to adjust the threshold voltage;    insulator spacers disposed against the sidewalls of the portion of said isolation regions that are above said semiconductor region and that taper so they are wider near said semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to said semiconductor region;    conductive floating gates spaced along said active regions, separated from said semiconductor region by a floating gate insulator layer, disposed between insulator spacers and extending about to the height of said isolation regions;    top gates comprised of conductive stripes perpendicular to said active regions, disposed over floating gates from which they are separated by a top gate insulator layer.    
     
     
         2 . The structure of  claim 1  wherein said isolation regions are oxide filled shallow trench isolation regions.  
     
     
         3 . The structure or  claim 1  wherein said semiconductor region is a silicon region.  
     
     
         4 . The structure of  claim 1  wherein said doping of the semiconductor region is accomplished by boron implantation at energy about 60 keV to a dose of about 2E13 per cm 2 .  
     
     
         5 . The structure of  claim 1  wherein said insulator spacers are composed of TEOS oxide.  
     
     
         6 . The structure of  claim 1  wherein said floating gate insulator layer is a thermally grown oxide about 90 Angstroms thick.  
     
     
         7 . The structure of  claim 1  wherein said conductive floating gates are composed of doped polysilicon.  
     
     
         8 . The structure of  claim 1  wherein said top gates are composed of doped polysilicon.  
     
     
         9 . The method of  claim 1  wherein said top gate insulator layer is an ONO layer with the bottom oxide layer being about 70 Angstroms thick, the nitride layer being about 160 Angstroms thick and the top oxide layer being about 40 Angstroms thick.  
     
     
         10 . A method of fabricating a structure to improve the coupling ratio of top gate to floating gate in flash memory cells, comprising: 
 providing a substrate containing a semiconductor region with an bare surface;    forming a pad first insulator layer over said semiconductor region surface;    forming a second insulator layer over said first insulator layer;    patterning said fist insulator layer and said second insulator layer to form parallel stripes that define areas that will be active regions;    etching trenches into exposed areas of said semiconductor region;    filling said trenches and the space above the trenches to the level of the top of the second insulator layer with isolation region insulation layers, thus forming isolation regions;    removing remaining second insulator layer;    performing ion implantation for threshold voltage adjustment;    forming insulator spacers against the sidewalls of said isolation regions that are wider near the semiconductor region and removing exposed first insulator layer;    forming a floating gate insulator layer over the exposed semiconductor region,    forming a floating gate conductor layer by filling, with conducting material, the space of the active regions between said oxide spacers to the level of the top of said isolation regions;    forming a top gate insulator layer;    forming a top gate conductor layer and patterning said top gate conductor layer to form parallel stripes perpendicular to the active regions, thus forming top gates;    removing top gate insulator layer and floating gate conductor layer that is not under said top gates.    
     
     
         11 . The method of  claim 10  wherein said first insulator layer is a pad oxide layer grown to a thickness of about 110 Angstroms.  
     
     
         12 . The method of  claim 10  wherein said second insulator layer is a nitride layer whose thickness is about 1600 Angstroms.  
     
     
         13 . The method of  claim 10  wherein said semiconductor region is a silicon region.  
     
     
         14 . The method of  claim 10  wherein said patterning of said first insulator layer and said second insulator layer is accomplished by forming a photoresist layer, patterning said photoresist layer and successively etching said first insulator layer and said second insulator layer and wherein said etching of trenches is accomplished before removal of said photoresist layer.  
     
     
         15 . The method of  claim 10  wherein filling of said trenches and the space above the trenches to the level of the top of the second insulator layer is accomplished by first forming a first isolation region insulator layer by growing a liner oxide of thickness about 200 Angstroms over sidewalls and bottoms of said trenches, than forming a second isolation region insulator layer by depositing about 6000 Angstroms of HDP oxide and performing CMP on said HDP oxide so its top level is about that of said second insulator level.  
     
     
         16 . The method of  claim 10  wherein removal or said remaining second insulator layer is accomplished by etching.  
     
     
         17 . The method of  claim 10  wherein said threshold voltage adjustment ion implantation is a boron ion implantation at energy about 60 keV at a dose of about 2E13 cm 2 .  
     
     
         18 . The method of  claim 10  wherein said insulator spacers are formed by depositing about 800 Angstroms of TEOS oxide and then performing a spacer etch that is maintained so that exposed first insulator layer is removed.  
     
     
         19 . The method of  claim 10  wherein said floating gate insulator layer is a grown oxide layer whose thickness is about 90 Angstroms.  
     
     
         20 . The method of  claim 10  wherein said floating gate conductor layer is composed of doped silicon that is deposited to a thickness of about 2000 Angstroms and etched back to the top lever of said isolation regions.  
     
     
         21 . The method of  claim 10  wherein said top gate insulator layer is an ONO layer with the bottom oxide layer being about 70 Angstroms thick, the nitride layer being about 160 Angstroms thick and the top oxide layer being about 40 Angstroms thick.  
     
     
         22 . The method of  claim 10  wherein said top gate conductor layer is formed of doped silicon deposited to a thickness of about 2500 Angstroms.  
     
     
         23 . The method of  claim 10  wherein said patterning of said top gate conductor layer is accomplished by forming a photoresist layer, patterning said photoresist layer and etching said top gate conductor layer and wherein exposed top gate insulator layer and floating gate conductor layer are removed by etching before said photoresist layer is removed.  
     
     
         24 . A structure to improve the coupling ratio of top gate to floating gate in flash memory cells, comprising: 
 parallel active regions, surrounded by isolation regions, over a semiconductor region of a substrate, said isolation regions having a portion within and a portion above said semiconductor region, and where the semiconductor region under said active regions is doped in the vicinity of the surface to adjust the threshold voltage;    insulator spacers disposed against the sidewalls of the portion of said isolation regions that are above said semiconductor region and that taper so they are wider near said semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to said semiconductor region;    conductive floating gates spaced along said active regions and electrically isolated from each other, separated from said semiconductor region by a floating gate insulator layer, disposed between insulator spacers and overlapping said isolation regions;    top gates comprised of conductive stripes perpendicular to said active regions, disposed over floating gates from which they are separated by a top gate insulator layer.    
     
     
         25 . The structure of  claim 24  wherein said isolation regions are oxide filled shallow trench isolation regions.  
     
     
         26 . The structure of  claim 24  wherein said semiconductor region is a silicon region.  
     
     
         27 . The structure of  claim 24  wherein said doping of the semiconductor region is accomplished by boron implantation at energy about 60 keV to a dose of about 2E13 per cm 2 .  
     
     
         28 . The structure of  claim 24  wherein said insulator spacers are composed of TEOS oxide.  
     
     
         29 . The structure of  claim 24  wherein said floating gate insulator layer is a thermally grown oxide about 90 Angstroms thick.  
     
     
         30 . The structure of  claim 24  wherein said conductive floating gates are composed of doped polysilicon.  
     
     
         31 . The structure of  claim 24  wherein said top gates are composed of doped polysilicon.  
     
     
         32 . The method of  claim 24  wherein said top gate insulator layer is an ONO layer with the bottom oxide layer being about 70 Angstroms thick, the nitride layer being about 160 Angstroms thick and the top oxide layer being about 40 Angstroms thick.  
     
     
         33 . A method of fabricating a structure to improve the coupling ratio of top gate to floating gate in flash memory cells, comprising: 
 providing a substrate containing a semiconductor region with an bare surface;    forming a pad first insulator layer over said semiconductor region surface;    forming a second insulator layer over said first insulator layer;    patterning said fist insulator layer and said second insulator layer to form parallel stripes that define areas that will be active regions;    etching trenches into exposed areas of said semiconductor region;    filling said trenches and the space above the trenches to the level of the top of the second insulator layer with isolation region insulation layers, thus forming isolation regions;    removing remaining second insulator layer;    performing ion implantation for threshold voltage adjustment;    forming insulator spacers against the sidewalls of said isolation regions that are wider near the semiconductor region and removing exposed first insulator layer;    forming a floating gate insulator layer over the exposed semiconductor region,    forming a floating gate conductor layer by depositing conducting material, filling the space of the active regions between said oxide spacers and extending to a level higher than the top of said isolation regions;    patterning said floating gate conducting layer to form electrically isolated stripes disposed over said active regions and overlapping neighboring isolation regions;    forming a top gate insulator layer;    forming a top gate conductor layer and patterning said top gate conductor layer to form parallel stripes perpendicular to the active regions, thus forming top gates;    removing top gate insulator layer and floating gate conductor layer that is not under said top gates.    
     
     
         34 . The method of  claim 33  wherein said first insulator layer is a pad oxide layer grown to a thickness of about 110 Angstroms.  
     
     
         35 . The method of  claim 33  wherein said second insulator layer is a nitride layer whose thickness is about 1600 Angstroms.  
     
     
         36 . The method of  claim 33  wherein said semiconductor region is a silicon region.  
     
     
         37 . The method of  claim 33  wherein said patterning of said first insulator layer and said second insulator layer is accomplished by forming a photoresist layer, patterning said photoresist layer and successively etching said first insulator layer and said second insulator layer and wherein said etching of trenches is accomplished before removal of said photoresist layer.  
     
     
         38 . The method of  claim 33  wherein filling of said trenches and the space above the trenches to the level of the top of the second insulator layer is accomplished by first forming a first isolation region insulator layer by growing a liner oxide of thickness about 200 Angstroms over sidewalls and bottoms of said trenches, than forming a second isolation region insulator layer by depositing about 6000 Angstroms of HDP oxide and performing CMP on said HDP oxide so its top level is about that of said second insulator level.  
     
     
         39 . The method of  claim 33  wherein removal of said remaining second insulator layer is accomplished by etching.  
     
     
         40 . The method of  claim 33  wherein said threshold voltage adjustment ion implantation is a boron ion implantation at energy about 60 keV at a dose of about 2E13 cm −2 .  
     
     
         41 . The method of  claim 33  wherein said insulator spacers are formed by depositing about 800 Angstroms of TEOS oxide and then performing a spacer etch that is maintained so that exposed first insulator layer is removed.  
     
     
         42 . The method of  claim 33  wherein said floating gate insulator layer is a grown oxide layer whose thickness is about 90 Angstroms.  
     
     
         43 . The method of  claim 33  wherein said floating gate conductor layer is composed of doped silicon that is deposited to a thickness of about 2000 Angstroms.  
     
     
         44 . The method of  claim 33  wherein said patterning of said floating gate conductor layer is accomplished by forming a photoresist layer, patterning said photoresist layer and etching said photoresist layer.  
     
     
         45 . The method of  claim 33  wherein said top gate insulator layer is an ONO layer with the bottom oxide layer being about 70 Angstroms thick, the nitride layer being about 160 Angstroms thick and the top oxide layer being about 40 Angstroms thick.  
     
     
         46 . The method of  claim 33  wherein said top gate conductor layer is formed of doped silicon deposited to a thickness of about 2500 Angstroms.  
     
     
         47 . The method of  claim 33  wherein said patterning of said top gate conductor layer is accomplished by forming a photoresist layer, patterning said photoresist layer and etching said top gate conductor layer and wherein exposed top gate insulator layer and floating gate conductor layer are removed by etching before said photoresist layer is removed.