Sandwich composite dielectric layer yielding improved integrated circuit device reliability

Abstract

A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction, and an integrated circuit having formed therein the gap filling sandwich composite dielectric layer construction. To practice the method, there is first provided a substrate having formed thereover a patterned layer. There is then formed upon the patterned layer a first conformal dielectric layer through a first plasma enhanced chemical vapor deposition (PECVD) method employing a first radio frequency power optimized primarily to limit plasma induced damage to the substrate and the patterned layer. The first radio frequency power is also optimized secondarily to limit moisture permeation through the first conformal dielectric layer. There is then formed upon the first conformal dielectric layer a gap filling dielectric layer. Finally, there is formed upon the gap filling dielectric layer a second conformal dielectric layer through a second plasma enhanced chemical vapor deposition (PECVD) method employing a second radio frequency power optimized primarily to limit moisture permeation through the second conformal dielectric layer.

What is claimed is:  
     
         1 . A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction comprising: 
 providing a substrate;    forming upon the substrate a patterned layer;    forming upon the patterned layer a first conformal dielectric layer, the first conformal dielectric layer being formed through a first plasma enhanced chemical vapor deposition (PECVD) method employing a first radio frequency power optimized primarily to limit plasma induced damage to the substrate and the patterned layer, the first radio frequency power also being optimized secondarily to limit moisture permeation through the first conformal dielectric layer;    forming upon the first conformal dielectric layer a gap filling dielectric layer; and    forming upon the gap filling dielectric layer a second conformal dielectric layer, the second conformal dielectric layer being formed through a second plasma enhanced chemical vapor deposition (PECVD) method employing a second radio frequency power optimized primarily to limit moisture permeation through the second conformal dielectric layer.    
     
     
         2 . The method of  claim 1  wherein the first conformal dielectric layer is formed from a silicon oxide dielectric material deposited through the first plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate as a silicon source material.  
     
     
         3 . The method of  claim 2  wherein the first radio frequency power is from about 400 to about 600 watts at a radio frequency of 13.56 MHZ.  
     
     
         4 . The method of  claim 3  wherein the first conformal dielectric layer is formed to a thickness of from about 1000 to about 2000 angstroms.  
     
     
         5 . The method of  claim 1  wherein the gap filling dielectric layer is formed from a silicon oxide gap filling dielectric layer chosen from the group of silicon oxide gap filling dielectric layers consisting of spin-on-glass (SOG) silicon oxide gap filling dielectric layers, ozone assisted atmospheric pressure chemical vapor deposited (APCVD) silicon oxide gap filling dielectric layers and ozone assisted sub-atmospheric pressure chemical vapor deposited (SACVD) silicon oxide gap filling dielectric layers.  
     
     
         6 . The method of  claim 1  wherein the second conformal dielectric layer is formed from a silicon oxide dielectric material deposited through the second plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material.  
     
     
         7 . The method of  claim 6  wherein the second radio frequency power is from about 600 to about 800 watts at a radio frequency of 13.56 MHZ.  
     
     
         8 . The method of  claim 7  wherein the second conformal dielectric layer is formed to a thickness of from about 17000 to about 21000 angstroms.  
     
     
         9 . The method of  claim 1  further comprising planarizing the second conformal dielectric layer to form a gap filling and planarizing sandwich composite dielectric layer construction, the planarizing yielding from the second conformal dielectric layer a second planarized dielectric layer of thickness from about 2000 to about 6000 angstroms.  
     
     
         10 . The method of  claim 1  further comprising forming at least one field effect transistor (FET) within and upon the substrate.  
     
     
         11 . An integrated circuit having formed therein a gap filling sandwich composite dielectric layer construction comprising: 
 a substrate;    a patterned layer formed over the substrate;    a first conformal dielectric layer formed upon the patterned layer, the first conformal dielectric layer being formed through a first plasma enhanced chemical vapor deposition (PECVD) method at a first radio frequency power chosen primarily to limit damage to the patterned layer and the substrate, the first radio frequency power also being chosen secondarily to limit moisture permeation through the first conformal dielectric layer;    a gap filling dielectric layer formed upon the first conformal dielectric layer; and    a second dielectric layer formed upon the gap filling dielectric layer, the second dielectric layer being formed through a second plasma enhanced chemical vapor deposition (PECVD) method at a second radio frequency power chosen primarily to limit moisture permeability through the second conformal dielectric layer.    
     
     
         12 . The integrated circuit of  claim 11  wherein the first conformal dielectric layer is formed from a silicon oxide dielectric material deposited through the first plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material.  
     
     
         13 . The integrated circuit of  claim 12  wherein the first radio frequency power is from about 400 to about 600 watts at a radio frequency of 13.56 MHZ.  
     
     
         14 . The integrated circuit of  claim 13  wherein the first conformal dielectric layer is formed to a thickness of from about 1000 to about 2000 angstroms.  
     
     
         15 . The integrated circuit of  claim 11  wherein the gap filling dielectric layer is formed from a silicon oxide gap filling dielectric material chosen from the group of silicon oxide gap filling dielectric materials consisting of spin-on-glass (SOG) silicon oxide gap filling dielectric materials, ozone assisted atmospheric pressure chemical vapor deposited (APCVD) silicon oxide gap filling dielectric materials and ozone assisted sub-atmospheric pressure chemical vapor deposited (SACVD) silicon oxide gap filling dielectric materials.  
     
     
         16 . The integrated circuit of  claim 11  wherein the second dielectric layer is formed from a silicon oxide dielectric material deposited through the second plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material.  
     
     
         17 . The integrated circuit of  claim 16  wherein the second radio frequency power is from about 600 to about 800 watts at a radio frequency of 13.56 MHZ.  
     
     
         18 . The integrated circuit of  claim 17  wherein the second dielectric layer is a second conformal dielectric layer formed to a thickness of from about 17000 to about 21000 angstroms.  
     
     
         19 . The integrated circuit of  claim 17  wherein the second dielectric layer is a second planarized dielectric layer formed to a thickness of from about 2000 to about 6000 angstroms.  
     
     
         20 . The integrated circuit of  claim 11  further comprising at least one field effect transistor (FET) formed within and upon the substrate.