Semiconductor device and method of manufacturing the same

Abstract

The present invention discloses structure and manufacturing method of binary nitride-oxide (NO) dielectric node for deep trench based DRAM devices. In the present invention, a thin strained SiGe layer is deposited prior to poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between buried plate and poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature.

1 . A method for manufacturing a semiconductor device, comprising the steps of: 
 (a) forming a trench in a substrate;    (b) forming a recessed arsenic silicate glass (ASG) in the trench;    (c) depositing an oxide layer covering the ASG recess in the trench;    (d) forming a buried plate in the substrate;    (e) removing the oxide layer and the ASG in the trench;    (f) forming a dielectric layer in the trench;    (g) depositing a thin strained layer in the trench; and    (h) filling a poly filler in the trench.    
     
     
         2 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the semiconductor device is a DRAM.  
     
     
         3 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the substrate is a silicon substrate.  
     
     
         4 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein step (b) comprises the steps of depositing an ASG layer in the trench and recessing the ASG layer in the trench.  
     
     
         5 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the buried plate is formed by an annealling process.  
     
     
         6 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the oxide layer and the ASG recess in the trench are removed by etching.  
     
     
         7 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the dielectric layer is a NO layer.  
     
     
         8 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein step (f) comprises the steps of depositing a nitride layer and re-oxidizing the nitride layer.  
     
     
         9 . The method for manufacturing a semiconductor device as claimed in  claim 8 , wherein the step of depositing the nitride layer is performed by LPCVD.  
     
     
         10 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the thin strained layer is a SiGe layer of a thickness less than 50 angstroms.  
     
     
         11 . The method for manufacturing a semiconductor device as claimed in  claim 10 , wherein the SiGe layer is of a formula Si x Ge 1−x  and has an energy gap (Eg) of 0.67 eV when x=1 and an energy gap (Eg) of 1.1 eV when x=0.  
     
     
         12 . The method for manufacturing a semiconductor device as claimed in  claim 1 , wherein the poly filler is an As poly filler.  
     
     
         13 . A semiconductor device, comprising 
 a substrate;    a trench in the substrate;    a buried plate in the substrate adjacent the trench;    a dielectric layer overlaying the trench;    a thin strained layer overlaying the dielectric layer; and    a poly filler in the trench.    
     
     
         14 . The semiconductor device as claimed in  claim 13 , wherein the semiconductor device is a DRAM.  
     
     
         15 . The semiconductor device as claimed in  claim 13 , wherein the dielectric layer is a NO layer.  
     
     
         16 . The semiconductor device as claimed in  claim 15 , wherein the NO layer is formed by depositing a nitride layer and re-oxidizing the nitride layer.  
     
     
         17 . The semiconductor device as claimed in  claim 13 , wherein the thin strained layer is a SiGe layer of a thickness less than 50 angstroms.  
     
     
         18 . The semiconductor device as claimed in  claim 17 , wherein the SiGe layer is of a formula Si x Ge 1−x  and has an energy gap (Eg) of 0.67 eV when x=1.  
     
     
         19 . The semiconductor device as claimed in  claim 13 , wherein the poly filler is an As poly filler.