Method for improving the electrical isolation between the contact and gate in a self-aligned contact mosfet device structure

Abstract

A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

What is claimed is:  
     
         1 . An improved method of fabricating a polycide self-aligned contact structure for MOSFET devices in a SRAM cell on a semiconductor substrate in which the electrical isolation between the contact and the gate structure is improved comprising; 
 forming a gate insulator layer on the semiconductor substrate,    depositing a first polysilicon layer on said gate insulator layer,    depositing a first metal silicide layer on said first polysilicon layer,    depositing a first insulator layer on said first metal silicide layer.    patterning said first insulator layer,    dip etching the exposed metal silicide layer in an isotropic etchant for metal silicide to form an undercut beneath the overlying edge of said first insulator layer,    continuing the patterning of said first metal silicide layer and said first polysilicon layer to form openings that define polycide gate structures on said gate insulator layer,    ion implanting a first conductivity imparting dopant into said semiconductor through said openings in regions not covered by said polycide gate structures to form lightly doped source and drain regions,    depositing a second insulator layer on said substrate that extends into said openings formed by the patterning, and into said undercut in said metal silicide layer,    anisotropically etching said second insulator layer to form sidewall spacers on the sides of said polycide gate structure,    ion implanting a second conductivity imparting dopant into said semiconductor substrate to form heavily doped source and drain regions,    depositing a third insulator layer,    opening a hole in said third insulator layer thereby forming a self-aligned SAC opening and exposing said heavily doped source and drain regions in the space defined by said sidewall spacers,    depositing a thin second polysilicon layer in contact with said heavily doped source and drain regions and said sidewall spacers,    depositing a thin second metal silicide layer over said second polysilicon layer,    patterning said second metal silicide layer and said second polysilicon layer to create a SAC structure.    
     
     
         2 . The method of  claim 1  which contains the further steps of completing the device structure by; 
 depositing a dielectric layer over the surface with openings over the contact structures, forming a metal plugs in the openings, and forming and interconnect metallization structure joining said metal plugs.  
 
     
     
         3 . The method of  claim 2  wherein said metal silicide is tungsten silicide.  
     
     
         4 . The method of  claim 3  wherein said dip etchant removes approximately 300 Angstroms from the surface of said tungsten silicide layer.  
     
     
         5 . The method of  claim 4  wherein the undercut extends approximately 200 Angstroms into said tungsten silicide layer.  
     
     
         6 . The method of  claim 5  wherein said isotropic etchant for tungsten silicide is comprised of 1 part NH 4 OH, 1 part H 2 O 2 , and 5 parts H 2 O, by volume.  
     
     
         7 . The method of  claim 6  wherein said tungsten silicide layer is exposed to said etchant for a time in the range of 20 to 25 minutes.  
     
     
         8 . The method of  claim 7  wherein said etchant is maintained at a temperature in the range of 25 to 35 degrees C.  
     
     
         9 . The method of  claim 1  wherein said metal silicide layer is tungsten silicide, deposited using LPCVD procedures at a temperature between 400 to 600 C., to a thickness between 750 to 1500 Angstroms, using silane and tungsten hexafluoride as a source.  
     
     
         10 . The method of  claim 9  wherein said polycide gate structures are patterned with an anistropic reactive ion etch (RIE), using CHF 3  as an etchant for said first insulator layer and using CL 2  as an etchant for said first metal silicide layer, and for said first polysilicon layer.  
     
     
         11 . The method of  claim 10  wherein said insulator spacers formed on said sides of said polycide gate structures are comprised of silicon nitride, deposited using LPCVD or plasma enhanced chemical vapor deposition procedures, to a thickness between 600 to 800 Angstroms, and etched with anisotropy RIE procedures, using CHF 3  as and etchant.  
     
     
         12 . The method of  claim 11  wherein said first insulator layer is silicon nitride having a thickness in the range of 2000 to 3000 Angstroms.  
     
     
         13 . The method of  claim 12  wherein said silicon nitride is reactively ion etched using CHF3 as an etchant.  
     
     
         14 . The method of  claim 1  wherein said first insulator layer is silicon oxide.  
     
     
         15 .An improved integrated circuit device which includes a self aligned contact between two gate structures on a semiconductor, wherein improved electrical isolation between the contact and gate structures is achieved comprising, 
 spaced gate structures, each having a bottom gate oxide layer, an overlying polysilicon layer, an overlying metal silicide layer, and a top insulating layer,    an undercut in said metal silicide layer underlying the lower edge of said top insulating layer,    sidewall spacers of insulating material defining a source/drain contact opening, and covering the vertical edge surfaces of said polysilicon layer, said metal silicide layer, and-said top insulating layer, said spacers extending into said undercut in said metal silicide layer,    source/drain regions in said semiconductor substrate underlying said opening, and    a conductive source/drain contact in said opening in contact with said sidewall spacers.    
     
     
         16 . The device of claim  15  wherein said metal silicide layer is tungsten silicide.  
     
     
         17 . The device of  claim 16  wherein said tungsten silicide layer has a thickness in the range of 1000 to 1200 Angstroms.  
     
     
         18 . The device of claim  15  wherein said undercut extends into said metal silicide layer to a depth in the range of 200 to 350 Angstrom.