Method of doping copper metallization

Abstract

This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electrochemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.

What is claimed is:  
     
         1 . A method of fabricating an integrated circuit on a substrate, the method comprising: 
 providing a substrate or substrate module;    providing a substrate having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line layer, or device contact region to P-N junctions;    providing a first level of conducting wiring being defined and embedded in a first layer of insulator;    providing patterned and etched via holes and trenches (channels) in deposited insulating material;    depositing (blanket) a thin via hole and trench barrier liner material which is a diffusion barrier;    depositing (alternate Method #1) an alloyed thin seed layer by physical vapor deposition (PVD) followed by chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper;    depositing (alternate Method #2) a thick layer of pure copper by chemical vapor deposition (CVD) or electrochemical deposition (ECD) followed by an alloyed layer by physical vapor deposition (PVD);    annealing by separate low temperature annealing steps (for said Methods #1 and #2 above) to enhance copper alloy formation;    polishing the excess conducting metal back by chemical mechanical polishing (CMP) and repeating the above process steps to make multilevel conducting layers by this integrated method.    
     
     
         2 . The method of  claim 1 , wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.  
     
     
         3 . The method of  claim 1 , wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.  
     
     
         4 . The method of  claim 1 , wherein the thin conformal alloyed seed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).  
     
     
         5 . The method of  claim 1 , wherein the chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface, thickness range from about 3,000 to 15,000 Angstroms.  
     
     
         6 . The method of  claim 1 , wherein the planar alloyed layer, thickness from about 500 to 5,000 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).  
     
     
         7 . The method of  claim 1 , wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.  
     
     
         8 . The method of  claim 1 , wherein the conducting structures are fabricating by repeating the integrated process described herein.  
     
     
         9 . The method of  claim 1 , wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.  
     
     
         10 . The method of  claim 1 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.  
     
     
         11 . The method of  claim 1 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.  
     
     
         12 . A method of fabricating an integrated circuit on a substrate to form alloyed copper interconnect lines and vias (said alternate Method #1) comprising the following steps: 
 providing a substrate or substrate module with integrated circuits therein;    providing a substrate having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line layer, or device contact region to P-N junctions;    providing a first level of conducting wiring being defined and embedded in a first layer of insulator;    providing patterned and etched via holes and trenches (channels) in deposited insulating material;    depositing (blanket) a thin via hole and trench barrier liner material, e.g., TaN, TiN, WN, which is a diffusion barrier;    depositing an alloyed thin conformal copper seed layer, e.g., Zr, Al, Ti, Sn, Zn, Mg, by physical vapor deposition (PVD), sputtering from an alloyed target;    depositing by chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper, planarizing the surface;    annealing by a special low temperature annealing step to enhance copper alloy formation of metal stack;    polishing the excess conducting metal back by chemical mechanical polishing (CMP) and repeating the above process steps to make multilevel conducting layers, which are corrosion/oxidation and electromigration resistant, by this integrated method.    
     
     
         13 . The method of  claim 12 , wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.  
     
     
         14 . The method of  claim 12 , wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.  
     
     
         15 . The method of  claim 12 , wherein the thin conformal alloyed seed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).  
     
     
         16 . The method of  claim 12 , wherein the chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface and is in a thickness range from about 3,000 to 15,000 Angstroms.  
     
     
         17 . The method of  claim 12 , wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.  
     
     
         18 . The method of  claim 12 , wherein the conducting structures are fabricating by repeating the integrated process described herein.  
     
     
         19 . The method of  claim 12 , wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.  
     
     
         20 . The method of  claim 12 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.  
     
     
         21 . The method of  claim 12 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.  
     
     
         22 . A method of fabricating an integrated circuit on a substrate to form alloyed copper interconnect lines and vias (said alternate Method #2) comprising the following: 
 providing a substrate or substrate module with integrated circuits therein;    providing a substrate having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line layer, or device contact region to P-N junctions;    providing a first level of conducting wiring being defined and embedded in a first layer of insulator;    providing patterned and etched via holes and trenches (channels) in deposited insulating material;    depositing (blanket) a thin via hole and trench barrier liner material, e.g., TaN, TiN, WN, which is a diffusion barrier;    depositing by chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper, planarizing the surface;    depositing an alloyed planar copper layer, e.g., Zr, Al, Ti, Sn, Zn, Mg, by physical vapor deposition (PVD), sputtering from an alloyed target;    annealing by a special low temperature annealing step to enhance copper alloy formation of metal stack;    polishing the excess conducting metal back by chemical mechanical polishing (CMP) and repeating the above process steps to make multilevel conducting layers, which are corrosion/oxidation and electromigration resistant, by this integrated method.    
     
     
         23 . The method of  claim 22 , wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.  
     
     
         24 . The method of  claim 22 , wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.  
     
     
         25 . The method of  claim 22 , wherein the chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface and is in a thickness range from about 3,000 to 15,000 Angstroms.  
     
     
         26 . The method of  claim 22 , wherein the planar alloyed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).  
     
     
         27 . The method of  claim 22 , wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.  
     
     
         28 . The method of  claim 22 , wherein the conducting structures are fabricating by repeating the integrated process described herein.  
     
     
         29 . The method of  claim 22 , wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.  
     
     
         30 . The method of  claim 22 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.  
     
     
         31 . The method of  claim 22 , wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.