Compliant integrated circuit package

Abstract

Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.

1 . A method of manufacturing a semiconductor device comprising the steps of: 
 (a) preparing a semiconductor chip having a plurality of semiconductor elements and a row of external terminals on a main surface thereof;    (b) preparing a wiring substrate having a wiring substrate base, a first array of bump lands, a scond array of bump lands, the wiring substrate base being provided with an opening positioned between the first and second array of bump lands, and a plurality of leads respectively forming bridge connections between at least one of the first array of bump lands and at least one of the second array of bump lands over the opening;    (c) positioning the wiring substrate over the main surface of the semiconductor chip such that the opening is positioned over the row of external terminals;    (d) cutting the plurality of leads at respective portions thereof over the opening and bonding each of the plurality of leads on corresponding ones of the external terminals through the opening, respectively.    
     
     
         2 . A method of manufacturing a semiconductor device according to  claim 1 , further comprising the steps of: 
 (e) sealing the row of external terminals and the plurality of leads bonded with the external terminals by potting method through the opening.    
     
     
         3 . A method of manufacturing a semiconductor device according to  claim 1 , 
 wherein each of the plurality of leads has a notch located at the bridging portion thereof over the opening, and    wherein, in step (d), each of the plurality of leads is cut at the notch thereof.    
     
     
         4 . A method of manufacturing a semiconductor device according to  claim 1 , wherein the minimum interval of the external terminals is smaller than the minimum interval of the bump lands.  
     
     
         5 . A method of manufacturing a semiconductor device according to  claim 1 , wherein, in step (c), the wiring substrate is positioned over the main surface of the semiconductor chip through an elastic layer.  
     
     
         6 . A method of manufacturing a semiconductor device according to  claim 1 , further comprising a step of: 
 (e) providing bump electrodes on each of the bump lands of the first and second array of bump lands, respectively.    
     
     
         7 . A method of manufacturing a semiconductor device according to  claim 5 , 
 wherein each of the plurality of leads has a notch located at the bridging portion thereof over the opening, and    wherein, in step (d), each of the plurality of leads is cut at the notch thereof.    
     
     
         8 . A method of manufacturing a semiconductor device according to  claim 7 , further comprising the steps of: 
 (e) sealing the row of external terminals and the plurality of leads bonded with the external terminals by potting method through the opening.    
     
     
         9 . A method of manufacturing a semiconductor device according to  claim 8 , further comprising a step of: 
 (f) providing bump electrodes on each of the bump lands of the first and second array of bump lands, respectively.    
     
     
         10 . A method of manufacturing a semiconductor device according to  claim 5 , wherein the minimum interval of the external terminals is smaller than the minimum interval of the bump lands.  
     
     
         11 . A method of manufacturing a semiconductor device comprising the steps of: 
 (a) preparing a semiconductor chip having a plurality of semiconductor elements and a row of external terminals on a main surface thereof;    (b) preparing a wiring substrate having a wiring substrate base, a first array of bump lands, a scond array of bump lands, the wiring substrate base being provided with an opening positioned between the first and second array of bump lands, and a plurality of leads respectively forming bridge connections between at least one of the first array of bump lands and at least one of the second array of bump lands over the opening;    (c) positioning the wiring substrate over the main surface of the semiconductor chip such that the opening is positioned over the row of external terminals;    (d) separating the plurality of leads at respective portions thereof over the opening and bonding each of the plurality of leads on corresponding ones of the external terminals through the opening, respectively.    
     
     
         12 . A method of manufacturing a semiconductor device according to  claim 11 , further comprising the steps of: 
 (e) sealing the row of external terminals and the plurality of leads bonded with the external terminals by encapsulation.    
     
     
         13 . A method of manufacturing a semiconductor device according to  claim 11 , 
 wherein each of the plurality of leads has a notch located at the bridging portion thereof over the opening, and    wherein, in step (d), each of the plurality of leads is separated at the notch thereof.    
     
     
         14 . A method of manufacturing a semiconductor device according to  claim 11 , wherein the minimum interval of the external terminals is smaller than the minimum interval of the bump lands.  
     
     
         15 . A method of manufacturing a semiconductor device according to  claim 11 , wherein, in step (c), the wiring substrate is positioned over the main surface of the semiconductor chip through an elastic layer.  
     
     
         16 . A method of manufacturing a semiconductor device according to  claim 11 , further comprising a step of: 
 (e) providing bump electrodes on each of the bump lands of the first and second array of bump lands, respectively.    
     
     
         17 . A method of manufacturing a semiconductor device according to  claim 15 , 
 wherein each of the plurality of leads has a notch located at the bridging portion thereof over the opening, and    wherein, in step (d), each of the plurality of leads is separated at the notch thereof.    
     
     
         18 . A method of manufacturing a semiconductor device according to  claim 17 , further comprising the steps of: 
 (e) sealing the row of external terminals and the plurality of leads bonded with the external terminals by encapsulation.    
     
     
         19 . A method of manufacturing a semiconductor device according to  claim 18 , further comprising a step of: 
 (f) providing bump electrodes on each of the bump lands of the first and second array of bump lands, respectively.    
     
     
         20 . A method of manufacturing a semiconductor device according to  claim 15 , wherein the minimum interval of the external terminals is smaller than the minimum interval of the bump lands.