Semiconductor memory device with sidewalls

Abstract

To provide a semiconductor memory device in which no separation of a silicide layer formed on a control gate takes place and a process for manufacturing the same. A gate dielectric layer and floating gate ( 4 in FIG. 4) are formed on a silicon substrate. A sidewall made of polysilicon ( 7 in FIG. 4) is disposed on the lateral side of the floating gate in such a manner that a stop oxide layer ( 6 a in FIG. 4) which functions as an etching stop for the polysilicon is sandwiched between the floating gate and the sidewall. A control gate (8 in FIG. 4) is laminated on the upper side of the floating gate having a step which is sloped by the sidewall in such a manner that an ONO layer ( 5 in FIG. 4) is sandwiched between the floating gate and the control gate.

What is claimed is:  
     
         1 . A semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of said control gate, wherein 
 a sidewall which is formed of a plurality members is disposed on a lateral wall of said floating gate.    
     
     
         2 . A semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of said control gate, wherein 
 a sidewall which is formed of a plurality members containing an electrically conductive material is disposed on a lateral wall of said floating gate.    
     
     
         3 . A semiconductor memory device as defined in  claim 1 , wherein 
 said plurality of members comprise a silicon oxide layer and polysilicon.    
     
     
         4 . A semiconductor memory device as defined in  claim 2 , wherein 
 said plurality of members comprise a silicon oxide layer and polysilicon.    
     
     
         5 . A semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of said control gate, wherein 
 a sidewall comprising a first and second members which are in contact with the lateral wall of said floating gate is disposed on a lateral wall of said floating gate, and    wherein said first member functions as an etching stop for said second member.    
     
     
         6 . A semiconductor memory device as defined in  claim 5 , wherein said first member comprises said silicon oxide layer and said second member comprises polysilicon.  
     
     
         7 . A semiconductor memory device as defined in  claim 3 , wherein said silicon oxide layer is formed by a thermal oxidation or chemical vapor deposition process.  
     
     
         8 . A semiconductor memory device as defined in  claim 6 , wherein said silicon oxide layer is formed by a thermal oxidation or chemical vapor deposition process.  
     
     
         9 . A semiconductor memory device as defined in  claim 6 , wherein said silicon oxide layer includes a naturally oxidized layer, which has such a thickness that said floating gate lateral wall is electrically connected with the second member.  
     
     
         10 . A semiconductor memory device as defined in  claim 1 , wherein said suicide layer comprises a titanium silicide layer.  
     
     
         11 . A semiconductor memory device as defined in  claim 2 , wherein said silicide layer comprises a titanium silicide layer.  
     
     
         12 . A semiconductor memory device as defined in  claim 5 , wherein said silicide layer comprises a titanium silicide layer.