Thin film capacitors on silicon germanium substrate and process for making the same

Abstract

An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

We claim:  
     
         1 . A high capacitance thin film capacitor device comprising: 
 a silicon germanium substrate; and    a capacitor, said capacitor comprising a bottom electrode, a top electrode, and a thin film of dielectric metal oxide between said electrodes.    
     
     
         2 . A high capacitance thin film capacitor device as in  claim 1  wherein said metal oxide comprises barium strontium titanate.  
     
     
         3 . A high capacitance thin film capacitor device as in  claim 2  wherein said barium strontium titan ate is represented by a chemical formula (Ba 1−x Sr x )TiO 3 , where 0<x<1.  
     
     
         4 . A high capacitance thin film capacitor device as in  claim 3  wherein said barium strontium titanate is represented by a chemical formula (Ba 0.7 Sr 0.3 )TiO 3 .  
     
     
         5 . A high capacitance thin film capacitor device as in  claim 1  wherein said metal oxide comprises a layered superlattice material.  
     
     
         6 . A high capacitance thin film capacitor device as in  claim 5  wherein said layered superlattice material is ferroelectric.  
     
     
         7 . A high capacitance thin film capacitor device as in  claim 5  wherein said layered superlattice material is nonferroelectric.  
     
     
         8 . A high capacitance thin film capacitor device as in  claim 1  wherein said metal oxide comprises a perovskite compounds.  
     
     
         9 . A high capacitance thin-film capacitor device as in  claim 8  wherein said perovskite compound is ferroelectric.  
     
     
         10 . A high capacitance thin film capacitor device as in  claim 8  wherein said perovskite compound is nonferroelectric.  
     
     
         11 . A high capacitance thin film capacitor device as in  claim 1 , further comprising a field oxide layer located directly on said silicon germanium substrate between said silicon germanium substrate and said bottom electrode.  
     
     
         12 . A high capacitance thin film capacitor device as in  claim 11  wherein said field oxide layer comprises silicon.  
     
     
         13 . A high capacitance thin film capacitor device as in  claim 11 , further comprising a diffusion barrier layer located on said field oxide layer between said field oxide layer and said bottom electrode.  
     
     
         14 . A high capacitance thin film capacitor device as in  claim 1 , further comprising a diffusion barrier layer located between said silicon germanium substrate and said bottom electrode.  
     
     
         15 . A high capacitance thin film capacitor device as in  claim 14  wherein said diffusion barrier layer comprises Si 3 N 4 .  
     
     
         16 . A high capacitance thin film capacitor device as in  claim 14  wherein said diffusion barrier layer is located directly on said silicon germanium substrate.  
     
     
         17 . A high capacitance thin film capacitor device as in  claim 14 , further comprising a stress reduction layer located between said diffusion barrier layer and said bottom electrode.  
     
     
         18 . A high capacitance thin film capacitor device as in  claim 17  wherein said stress reduction layer is located directly on said diffusion barrier layer.  
     
     
         19 . A high capacitance thin film capacitor device as in  claim 17  wherein said stress reduction layer comprises silicon dioxide.  
     
     
         20 . A high capacitance thin film capacitor device as in  claim 17  wherein said stress reduction layer comprises a glasseous oxide.  
     
     
         21 . A high capacitance thin film capacitor device as in  claim 1  wherein said bottom electrode comprises an adhesion layer and an electrode layer.  
     
     
         22 . A high capacitance thin film capacitor device as in  claim 21  wherein said adhesion layer comprises a material selected from the group consisting of titanium, tantalum, nickel, tantalum silicide, nickel silicide, and palladium.  
     
     
         23 . A high capacitance thin film capacitor device as in  claim 21  wherein said electrode layer comprises platinum.  
     
     
         24 . A high capacitance thin film capacitor device as in  claim 1 , further comprising a stress reduction layer located between said silicon germanium substrate and said bottom electrode.  
     
     
         25 . A high capacitance thin film capacitor device as in  claim 24  wherein said stress reduction layer is located directly on said silicon germanium substrate.  
     
     
         26 . A high capacitance thin film capacitor device as in  claim 24  wherein said stress reduction layer comprises silicon dioxide.  
     
     
         27 . A high capacitance thin film capacitor device as in  claim 24  wherein said stress reduction layer comprises a glasseous oxide.  
     
     
         28 . A high capacitance thin film capacitor device as in  claim 1  wherein said silicon germanium substrate comprises a silicon germanium wafer.  
     
     
         29 . A high capacitance thin film capacitor device as in  claim 1  wherein said silicon germanium substrate comprises a silicon semiconductor wafer.  
     
     
         30 . A high capacitance thin film capacitor device as in  claim 1  wherein said silicon germanium substrate comprises a silicon germanium region.  
     
     
         31 . A high capacitance thin film capacitor device as in  claim 30  wherein said silicon germanium region comprises a crystal lattice having relative amounts of silicon and germanium atoms represented by a stoichiometric formula Si 1−x Ge x , in which 0<x<1.  
     
     
         32 . A high capacitance thin film capacitor device as in  claim 30  wherein said silicon germanium region comprises a silicon germanium layer.  
     
     
         33 . A high capacitance thin film capacitor device as in  claim 1  wherein said silicon germanium substrate comprises a silicon germanium device portion.  
     
     
         34 . A high capacitance thin film capacitor device as in  claim 33  wherein said silicon germanium device portion comprises a heterojunction bipolar transistor.  
     
     
         35 . A high capacitance thin film capacitor device as in  claim 33  wherein said silicon germanium device portion comprises a BICMOS device.  
     
     
         36 . A high capacitance thin film capacitor device as in  claim 33  wherein said silicon germanium device portion comprises a MOSFET.  
     
     
         37 . A method of fabricating a high capacitance thin film capacitor device, said method comprising steps of: 
 providing a silicon germanium substrate;    forming a bottom electrode;    providing a liquid precursor for forming a thin film of dielectric metal oxide;    applying said liquid precursor to form a coating on said bottom electrode;    treating said coating on said bottom electrode to form said thin film of dielectric metal oxide; and    forming a top electrode on said thin film of dielectric metal oxide.    
     
     
         38 . A method as in  claim 37  wherein said step of applying comprises spinning said liquid precursor on said bottom electrode.  
     
     
         39 . A method as in  claim 37  wherein said step of treating comprises heating said coating on said electrode to a temperature of from 200° C. to 500° C.  
     
     
         40 . A method as in  claim 37  wherein said step of treating comprises heating the coating on said electrode to a temperature of about 400° C. in air or nitrogen gas.  
     
     
         41 . A method as in  claim 37  wherein said step of treating comprises annealing said coating on said electrode at a temperature of between 600° C. and 850° C.  
     
     
         42 . A method as in  claim 41  wherein said step of annealing comprises annealing at a temperature of about 700° C. in oxygen.  
     
     
         43 . A method as in  claim 37  wherein said step of treating comprises a first anneal of said thin film of dielectric metal oxide for a time between 1 minute and 90 minutes.  
     
     
         44 . A method as in  claim 43  and further including a second anneal of said thin film of dielectric metal oxide for a time between 1 minute and 90 minutes.  
     
     
         45 . A method as in  claim 37  wherein said step of treating comprises drying said liquid coating and further including the step of repeating said steps of applying said liquid precursor and drying said liquid coating one or more times until said thin film of dielectric metal oxide has a desired thickness.  
     
     
         46 . A method as in  claim 37  wherein said thin film of dielectric metal oxide comprises barium strontium titanate.  
     
     
         47 . A method as in  claim 46  wherein said barium strontium titanate has the formula Ba 0.7 Sr 0.3 TiO 3 .  
     
     
         48 . A method as in  claim 37  wherein said liquid precursor comprises a metal alkoxycarboxylate.  
     
     
         49 . A method as in  claim 48  wherein said liquid precursor further comprises a metal alkoxide.  
     
     
         50 . A method as in  claim 37 , further comprising a step of forming a diffusion barrier layer on said silicon germanium substrate before said step of forming a bottom electrode.  
     
     
         51 . A method as in  claim 50  wherein said diffusion barrier layer comprises Si 3 N 4 .  
     
     
         52 . A method as in  claim 51  wherein said Si 3 N 4  has a thickness of about 150 nm.  
     
     
         53 . A method as in  claim 50 , further comprising a step of forming a stress reduction layer between said steps of forming a diffusion barrier layer and forming a bottom electrode.  
     
     
         54 . A method as in  claim 53  wherein said stress reduction layer comprises silicon dioxide.  
     
     
         55 . A method as in  claim 54  wherein said silicon dioxide layer has a thickness of about 100 nm.  
     
     
         56 . A method as in  claim 53  wherein said stress reduction layer is formed directly on said diffusion barrier.  
     
     
         57 . A method as in  claim 37 , further comprising a step of forming a stress reduction layer on said silicon germanium substrate before said step of forming a bottom electrode.  
     
     
         58 . A method as in  claim 57  wherein said stress reduction layer comprises silicon dioxide.  
     
     
         59 . A method as in  claim 58  wherein said silicon dioxide layer has a thickness of about 100 nm.