US2002084032A1PendingUtilityA1

Multiple chamber vacuum processing system configuration for improving the stability of mark shielding process

Assignee: TAIWAN SEMICONDUCTOR MFGPriority: Feb 19, 1999Filed: Feb 26, 2002Published: Jul 4, 2002
Est. expiryFeb 19, 2019(expired)· nominal 20-yr term from priority
H10P 72/3304H10P 72/0461H10P 72/0454Y10S134/902Y10S438/908
38
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Claims

Abstract

A new configuration of a basic concatenatable integrated modular multiple chamber vacuum processing system for wafer manufacturing vacuum processes is disclosed. The basic system includes at least one multiple ported transfer vacuum chamber, an R-θ transfer means contained within each chamber, a multiplicity of ports adaptable for appending a variety of vacuum process chambers as well as forming entrance/exit ports with at least one dual port pass through chamber attached to one entrance/exit port. Each pass through chamber contains a wafer alignment and/or orientation means for aligning or orienting the wafer as necessary in any of the appended process chambers. The configuration minimizes alignment or orientation errors due to inherent instability of the concatenated transfer means operations.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method of processing a wafer made of semiconductor material within an integrated modular multiple chamber vacuum processing system requiring alignment of the wafer comprising the steps: 
 providing a first transfer chamber, a degas means, a cleaning means, and a first transfer means, together associated with the first transfer chamber, a second transfer chamber, a second transfer means, a processing means, and an alignment means, together associated with the second transfer chamber;    degas the wafer by the degas means;    cleaning the wafer by the cleaning means;    passing the wafer from the first transfer chamber to the second transfer chamber by sequential action of the first and second transfer means;    aligning the wafer by the alignment means; and    processing the wafer by the processing means.    
     
     
         2 . The method according to  claim 1  wherein the alignment means is located in a pass through chamber provided for transferring the wafer between the first and second transfer chambers.  
     
     
         3 . The method according to  claim 1  wherein the alignment means is an orientor responsive to a certain feature on the wafer, for orienting the wafer with respect to a position in the process chamber.  
     
     
         4 . The method according to  claim 3  wherein the certain feature is a notch in the periphery of the wafer.  
     
     
         5 . A configuration of modular components in a concatenated integrated modular multiple chamber vacuum processing system for processing a wafer made of semiconductor material requiring alignment for processing comprising: 
 a first transfer chamber having a plurality of ports, one of the ports serving as a closable entrance port, at least one of the ports serving as an exit port, and each of the remaining ports serving as process chamber ports;    a first transfer means located within the first transfer chamber for transferring the wafer through each of the plurality of ports of the first transfer chamber;    at least one second transfer chamber having a plurality of ports, one of the ports serving as an entrance port, and each of the remaining ports serving as a process chamber port;    a second transfer means located within each of the second transfer chambers for transferring the wafer through each of the plurality of ports in each of the second transfer chambers;    at least one dual port pass through chamber, including a wafer way station therein for holding the wafer between operations of the first and second transfer means, each dual port pass through chamber interposed between each first transfer chamber exit port and each second transfer chamber entrance port thereby providing communication between the first transfer chamber and each of the second transfer chambers;    a plurality of process chambers externally appended to the first and second transfer chambers, corresponding to each of the ports serving as processing chamber ports; and    an alignment means located at the wafer way station in at least one of the pass through chambers for aligning the wafer to with respect to a position in a proximate process chamber.    
     
     
         6 . A configuration of the processing system of  claim 5  wherein, each of the remaining ports of the second transfer chambers additionally serving as an exit port, at least one additional dual port pass through chambers being interposed between the exit port of the second transfer chamber and the entrance port of an additional second transfer chamber having at least one appended process chamber, thereby extending the concatenation to an additional level of second transfer chambers.  
     
     
         7 . A configuration of the processing system of  claim 6 , wherein the alignment means is located at the wafer way station in at least one of the additional pass through chambers proximate to the process chamber requiring alignment.  
     
     
         8 . A configuration of the processing system of  claim 5 , wherein the alignment means is an orientation means responsive to a certain fixed feature on the wafer.  
     
     
         9 . A configuration of the processing system of  claim 8  wherein the certain fixed feature is a notch in the periphery of the wafer.  
     
     
         10 . A configuration of the processing system of  claim 8  where the certain fixed feature is a mark in the surface of the wafer.  
     
     
         11 . A configuration of modular components in a monolithic dual transfer integrated modular multiple chamber vacuum processing system for processing a wafer made of semiconductor material requiring alignment for processing comprising: 
 a monolithic vacuum casing containing a first transfer chamber, a second transfer chamber, and at least one pass through chamber;    the first transfer chamber having a plurality of ports, one of the ports serving as a closable entrance port, at least one of the ports serving as a first pass through port to the pass through chamber, and each of the remaining ports serving as chamber ports;    a first transfer means located within the first transfer chamber for transferring the wafer through each of the plurality of ports of the first transfer chamber;    the second transfer chamber having a plurality of ports, at least one of the ports serving as a second pass through port to the pass through chamber, and each of the remaining ports serving as a process chamber port;    a second transfer means located within the second transfer chamber for transferring the wafer through each of the plurality of ports of the second transfer chamber;    a wafer way station contained within the pass through chamber for holding the wafer between operations of the first and the second transfer means,    a plurality of process chambers externally appended to the first and second transfer chambers; and    an alignment means associated with the second transfer chamber for aligning the wafer with respect to a position in the process chambers.    
     
     
         12 . A configuration of the processing system of  claim 11 , wherein the alignment means is located in an alignment chamber centrally appended to the second transfer chamber with respect to the process chambers.  
     
     
         13 . A configuration of the processing system of  claim 11 , wherein the alignment means is located at the way station in the pass through chamber.  
     
     
         14 . A configuration of the processing system of  claim 11 , wherein the alignment means is an orientation means responsive to a certain fixed feature on the semiconductor wafer.  
     
     
         15 . A configuration of the processing system of  claim 14  wherein the certain fixed feature is a notch in the periphery of the wafer.  
     
     
         16 . A configuration of the processing system of  claim 14  where the certain fixed feature is a mark in the surface of the wafer.  
     
     
         17 . A configuration of the processing system of  claim 11  having a second way station in a second pass through chamber served by a third and a fourth pass through port respectively located in the first and second transfer chambers for transferring the wafer between the second and first transfer chambers.

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