Inventor · disambiguated record
Reid A. Wistort
Also filed as: WISTORT REID · WISTORT REID A · WISTORT REID ALLEN
21 granted patents·1 pending application·368 citations·filing 1995–2012
96Inventor score
Top patents by PatentIndex Score
22 records- 0196US6373738B1Low power CAM match line circuitIBM·Filed 2000·Granted Apr 16, 2002·143 cites·16 claims
- 0291US8233302B2Content addressable memory with concurrent read and search/compare operations at the same memory cellARSOVSKI IGOR·Filed 2011·Granted Jul 31, 2012·14 cites·9 claims
- 0391US7924588B2Content addressable memory with concurrent two-dimensional search capability in both row and column directionsIBM·Filed 2007·Granted Apr 12, 2011·23 cites·21 claims
- 0481US7688611B2CAM asynchronous search-line switchingIBM·Filed 2008·Granted Mar 30, 2010·14 cites·17 claims
- 0580US7515449B2CAM asynchronous search-line switchingIBM·Filed 2006·Granted Apr 7, 2009·10 cites·16 claims
- 0679US6201750B1Scannable fuse latchesIBM·Filed 2000·Granted Mar 13, 2001·28 cites·19 claims
- 0777US6697277B2Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedancesIBM·Filed 2003·Granted Feb 24, 2004·22 cites·7 claims
- 0874US6618279B2Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)IBM·Filed 2001·Granted Sep 9, 2003·19 cites·15 claims
- 0969US6998897B2System and method for implementing a micro-stepping delay chain for a delay locked loopIBM·Filed 2004·Granted Feb 14, 2006·13 cites·19 claims
- 1067US9384835B2Content addressable memory early-predict late-correct single ended sensingARSOVSKI IGOR·Filed 2012·Granted Jul 5, 2016·3 cites·24 claims
- 1164US8218378B2Word-line level shift circuitARSOVSKI IGOR·Filed 2009·Granted Jul 10, 2012·5 cites·18 claims
- 1264US7049873B2System and method for implementing a micro-stepping delay chain for a delay locked loopIBM·Filed 2004·Granted May 23, 2006·10 cites·19 claims
- 1364US6791855B2Redundant array architecture for word replacement in CAMIBM·Filed 2003·Granted Sep 14, 2004·11 cites·6 claims
- 1459US8437201B2Word-line level shift circuitARSOVSKI IGOR·Filed 2012·Granted May 7, 2013·2 cites·9 claims
- 1557US6728123B2Redundant array architecture for word replacement in CAMIBM·Filed 2002·Granted Apr 27, 2004·8 cites·4 claims
- 1656US6396336B2Sleep mode VDD detune for power reductionIBM·Filed 2001·Granted May 28, 2002·8 cites·3 claims
- 1754US5638315AContent addressable memory for a data processing systemIBM·Filed 1995·Granted Jun 10, 1997·15 cites·20 claims
- 1848US7117400B2Memory device with data line steering and bitline redundancyIBM·Filed 2002·Granted Oct 3, 2006·5 cites·26 claims
- 1947US5918003AEnhanced built-in self-test circuit and methodIBM·Filed 1997·Granted Jun 29, 1999·12 cites·3 claims
- 2034US6333671B1Sleep mode VDD detune for power reductionIBM·Filed 1999·Granted Dec 25, 2001·3 cites·6 claims
- 2134US2008046789A1Apparatus and method for testing memory devices and circuits in integrated circuitsARSOVSKI IGOR·Filed 2006·Application pending·0 cites
- 2229US6356981B1Method and apparatus for preserving data coherency in a double data rate SRAMIBM·Filed 1999·Granted Mar 12, 2002·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →