Inventor · disambiguated record
Mark A. Zaleski
Also filed as: ZALESKI MARK · ZALESKI MARK A · ZALESKI MARK ALEXANDER
22 granted patents·3 pending applications·376 citations·filing 1994–2024
95Inventor score
Top patents by PatentIndex Score
25 records- 0198US9368395B1Self-aligned via and air gapGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 14, 2016·39 cites·16 claims
- 0294US9202751B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 1, 2015·13 cites·20 claims
- 0394US9117822B1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 25, 2015·16 cites·10 claims
- 0493US9263325B1Precut metal linesGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 16, 2016·12 cites·20 claims
- 0592US9679805B2Self-aligned back end of line cutGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 13, 2017·7 cites·14 claims
- 0691US9236437B2Method for creating self-aligned transistor contactsGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·11 cites·8 claims
- 0790US9508642B2Self-aligned back end of line cutGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 29, 2016·9 cites·17 claims
- 0886US5478436ASelective cleaning process for fabricating a semiconductor deviceMOTOROLA INC·Filed 1994·Granted Dec 26, 1995·138 cites·17 claims
- 0985US5916011AProcess for polishing a semiconductor device substrateMOTOROLA INC·Filed 1996·Granted Jun 29, 1999·66 cites·28 claims
- 1083US10833087B2Semiconductor devices including transistors comprising a charge trapping material, and related systems and methodsMICRON TECHNOLOGY INC·Filed 2018·Granted Nov 10, 2020·5 cites·27 claims
- 1181US9660040B2Transistor contacts self-aligned two dimensionsGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·2 cites·6 claims
- 1276US10396026B2Precut metal linesGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 27, 2019·2 cites·14 claims
- 1376US9842801B2Self-aligned via and air gapGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 12, 2017·2 cites·12 claims
- 1476US9362162B2Methods of fabricating BEOL interlayer structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 7, 2016·3 cites·20 claims
- 1575US10181420B2Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·2 cites·10 claims
- 1674US9502528B2Borderless contact formation through metal-recess dual cap integrationGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 22, 2016·3 cites·13 claims
- 1773US5707492AMetallized pad polishing processMOTOROLA INC·Filed 1995·Granted Jan 13, 1998·46 cites·8 claims
- 1871US2024147693A1Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devicesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1965US11903183B2Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devicesMICRON TECHNOLOGY INC·Filed 2020·Granted Feb 13, 2024·0 cites·22 claims
- 2059US10056373B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 21, 2018·0 cites·20 claims
- 2152US11696432B2Multi-direction conductive line and staircase contact for semiconductor devicesMICRON TECHNOLOGY INC·Filed 2020·Granted Jul 4, 2023·0 cites·7 claims
- 2252US9293363B2Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 22, 2016·0 cites·7 claims
- 2351US9461128B2Method for creating self-aligned transistor contactsGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·0 cites·7 claims
- 2449US2017025347A1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 2539US2009045164A1"universal" barrier cmp slurry for use with low dielectric constant interlayer dielectricsFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
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