Inventor · disambiguated record
Bob W. Verbruggen
Also filed as: VERBRUGGEN BOB · VERBRUGGEN BOB W
22 granted patents·106 citations·filing 2009–2023
93Inventor score
Top patents by PatentIndex Score
22 records- 0195US8384578B2Stochastic analog-to-digital (A/D) converter and method for using the sameIMEC·Filed 2011·Granted Feb 26, 2013·27 cites·10 claims
- 0293US11716089B1Delay-tracking biasing for voltage-to-time conversionXILINX INC·Filed 2022·Granted Aug 1, 2023·3 cites·20 claims
- 0391US10291247B1Chopping switch time-skew calibration in time-interleaved analog-to-digital convertersXILINX INC·Filed 2018·Granted May 14, 2019·10 cites·16 claims
- 0489US8957794B2A/D converter and method for calibrating the sameIMEC·Filed 2013·Granted Feb 17, 2015·13 cites·10 claims
- 0588US10483996B1Time skew calibration of time-interleaved analog to digital convertersXILINX INC·Filed 2018·Granted Nov 19, 2019·8 cites·18 claims
- 0687US10298248B1Differential offset calibration of chopping switches in time-interleaved analog-to-digital convertersXILINX INC·Filed 2018·Granted May 21, 2019·7 cites·20 claims
- 0786US10320401B2Dual-path digital-to-time converterXILINX INC·Filed 2017·Granted Jun 11, 2019·6 cites·18 claims
- 0885US8199043B2Comparator based asynchronous binary search A/D converterVAN DER PLAS GEERT·Filed 2009·Granted Jun 12, 2012·17 cites·11 claims
- 0979US10862500B1Embedded variable output power (VOP) in a current steering digital-to-analog converterXILINX INC·Filed 2019·Granted Dec 8, 2020·3 cites·20 claims
- 1079US9166608B1Method and circuit for bandwidth mismatch estimation in an A/D converterIMEC VZW·Filed 2015·Granted Oct 20, 2015·5 cites·8 claims
- 1176US10944414B1Method and apparatus for psuedo-random interleaved analog-to-digital converter useXILINX INC·Filed 2020·Granted Mar 9, 2021·1 cites·20 claims
- 1273US10379570B1Clock divide-by-three circuitXILINX INC·Filed 2018·Granted Aug 13, 2019·2 cites·20 claims
- 1372US10581450B1Embedded variable gain amplifier in a current steering digital-to-analog converterXILINX INC·Filed 2019·Granted Mar 3, 2020·2 cites·20 claims
- 1466US9349484B2Sample-and-hold circuit for an interleaved analog-to-digital converterIMEC VZW·Filed 2015·Granted May 24, 2016·2 cites·17 claims
- 1563US12191876B2Gain calibration with quantizer offset settingsXILINX INC·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 1658US12425036B2Mitigating gain mismatch interference in analog-to-digital converter circuitryXILINX INC·Filed 2023·Granted Sep 23, 2025·0 cites·20 claims
- 1755US11923856B2Low-latency time-to-digital converter with reduced quantization stepXILINX INC·Filed 2022·Granted Mar 5, 2024·0 cites·19 claims
- 1853US11323108B1Low current line termination structureXILINX INC·Filed 2020·Granted May 3, 2022·0 cites·16 claims
- 1950US11009597B2Phase noise compensation in digital beamforming radar systemsXILINX INC·Filed 2018·Granted May 18, 2021·0 cites·16 claims
- 2045US10969821B2Latency synchronization across clock domainsXILINX INC·Filed 2018·Granted Apr 6, 2021·0 cites·20 claims
- 2138US10886906B1Duty-cycle correction using balanced clocksXILINX INC·Filed 2018·Granted Jan 5, 2021·0 cites·18 claims
- 2229US8618973B2Interleaved pipelined binary search A/D converterVERBRUGGEN BOB·Filed 2010·Granted Dec 31, 2013·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →