Chopping switch time-skew calibration in time-interleaved analog-to-digital converters

Abstract

An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

What is claimed is: 
     
       1. A time-skew calibration circuit, comprising:
 a plurality of first circuits, each including a first accumulator and a second accumulator; 
 a plurality of second circuits, each including:
 a first adder coupled to outputs of the first accumulator and the second accumulator; 
 a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and 
 a decision circuit configured to combine an output of the first adder and an output of the first subtractor, the decision circuit comprising a second subtractor coupled to an output of the first adder, a first multiplier coupled to an output of the second subtractor, and a second multiplier coupled to an output of the first subtractor. 
 
 
     
     
       2. The time-skew calibration circuit of  claim 1 , wherein the decision circuit further comprises:
 a third accumulator coupled to outputs of the first and second multipliers; and 
 a fourth accumulator coupled to the outputs of the first and second multipliers. 
 
     
     
       3. The time-skew calibration circuit of  claim 1 , wherein each of the plurality of first circuits further includes:
 a third subtractor; 
 an absolute value circuit coupled to an output of the third subtractor; 
 a third multiplier coupled to an output of the absolute value circuit; and 
 a demultiplexer having an input coupled to an output of the third multiplier and outputs coupled to inputs of the first and second accumulators. 
 
     
     
       4. The time-skew calibration circuit of  claim 1 , further comprising:
 an average circuit coupled to the outputs of the first and second accumulators and to an input of the second subtractor. 
 
     
     
       5. The time-skew calibration circuit of  claim 2 , wherein each of the plurality of second circuits comprises:
 first and second rounding circuits respectively coupled to outputs of the third and fourth accumulators. 
 
     
     
       6. The time-skew calibration circuit of  claim 1 , further comprising:
 a plurality of correction circuits respectively coupled to outputs of the plurality of second circuits. 
 
     
     
       7. An analog-to-digital converter (ADC), comprising:
 a plurality of channels each including a chopping circuit; and 
 a time-skew calibration circuit coupled to the plurality of channels, comprising: 
 a plurality of first circuits, each including a first accumulator and a second accumulator; 
 a plurality of second circuits, each including:
 a first adder coupled to outputs of the first accumulator and the second accumulator; 
 a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and 
 
 a decision circuit configured to combine an output of the first adder and an output of the first subtractor, the decision circuit comprising a second subtractor coupled to an output of the first adder, a first multiplier coupled to an output of the second subtractor, and a second multiplier coupled to an output of the first subtractor. 
 
     
     
       8. The ADC of  claim 7 , wherein the decision circuit further comprises:
 a third accumulator coupled to outputs of the first and second multipliers; and 
 a fourth accumulator coupled to the outputs of the first and second multipliers. 
 
     
     
       9. The ADC of  claim 7 , wherein each of the plurality of first circuits further includes:
 a third subtractor; 
 an absolute value circuit coupled to an output of the third subtractor; 
 a third multiplier coupled to an output of the absolute value circuit; and 
 a demultiplexer having an input coupled to an output of the third multiplier and outputs coupled to inputs of the first and second accumulators. 
 
     
     
       10. The ADC of  claim 7 , further comprising:
 an average circuit coupled to the outputs of the first and second accumulators and to an input of the second subtractor. 
 
     
     
       11. The ADC of  claim 8 , wherein each of the plurality of second circuits comprises:
 first and second rounding circuits respectively coupled to outputs of the third and fourth accumulators. 
 
     
     
       12. The ADC of  claim 7 , further comprising:
 a plurality of correction circuits respectively coupled to outputs of the plurality of second circuits. 
 
     
     
       13. A method of time-skew calibration for a time-interleaved analog-to-digital converter (ADC), comprising:
 synchronizing a chopping sequence applied to chopping circuits in channels of the ADC to a time-skew calibration observation window; 
 inverting polarity of the chopping sequence half-way into the time-skew calibration observation window; and 
 executing a dual-loop time-skew calibration on outputs of the channels of the ADC by processing an output signal of the chopping circuits in each of the channels through a plurality of first circuits and a plurality of second circuits, each of the plurality of first circuits including a first accumulator and a second accumulator, each of the plurality of second circuits including: a first adder coupled to outputs of the first accumulator and the second accumulator; a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and a decision circuit configured to combine an output of the first adder and an output of the first subtractor, the decision circuit comprising a second subtractor coupled to an output of the first adder, a first multiplier coupled to an output of the second subtractor, and a second multiplier coupled to an output of the first subtractor. 
 
     
     
       14. The method of  claim 13 , wherein the step of synchronizing the chopping sequence comprises:
 repeating the chopping sequence an integer number of times in the time-skew calibration observation window. 
 
     
     
       15. The method of  claim 13 , wherein the decision circuit further comprises a third accumulator coupled to outputs of the first and second multipliers, and a fourth accumulator coupled to the outputs of the first and second multipliers. 
     
     
       16. The method of  claim 13 , wherein each of the plurality of first circuits further includes a third subtractor, an absolute value circuit coupled to an output of the third subtractor, a third multiplier coupled to an output of the absolute value circuit; and a demultiplexer having an input coupled to an output of the third multiplier and outputs coupled to inputs of the first and second accumulators.