Inventor · disambiguated record
Alwin Tsao
Also filed as: TSAO ALWIN · TSAO ALWIN J · TSAO ALWIN JAMES
25 granted patents·1 pending application·404 citations·filing 1998–2020
96Inventor score
Top patents by PatentIndex Score
26 records- 0196US8067279B2Application of different isolation schemes for logic and embedded memorySADRA KAYVAN·Filed 2009·Granted Nov 29, 2011·113 cites·5 claims
- 0288US7141480B2Tri-gate low power device and method for manufacturing the sameTEXAS INSTRUMENTS INC·Filed 2004·Granted Nov 28, 2006·45 cites·16 claims
- 0387US6143594AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 7, 2000·40 cites·5 claims
- 0486US7274046B2Tri-gate low power device and method for manufacturing the sameTEXAS INSTRUMENTS INC·Filed 2005·Granted Sep 25, 2007·13 cites·5 claims
- 0584US6693357B1Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformityTEXAS INSTRUMENTS INC·Filed 2003·Granted Feb 17, 2004·38 cites·63 claims
- 0682US7193277B2Application of different isolation schemes for logic and embedded memoryTEXAS INSTRUMENTS INC·Filed 2005·Granted Mar 20, 2007·7 cites·3 claims
- 0777US9202859B1Well resistors and polysilicon resistorsTEXAS INSTRUMENTS INC·Filed 2014·Granted Dec 1, 2015·3 cites·10 claims
- 0875US7314800B2Application of different isolation schemes for logic and embedded memoryTEXAS INSTRUMENTS INC·Filed 2005·Granted Jan 1, 2008·4 cites·4 claims
- 0973US6162728AMethod to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applicationsTEXAS INSTRUMENTS INC·Filed 1999·Granted Dec 19, 2000·41 cites·16 claims
- 1071US6137144AOn-chip ESD protection in dual voltage CMOSTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 24, 2000·27 cites·6 claims
- 1170US7250334B2Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrodeTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 31, 2007·17 cites·20 claims
- 1270US7045436B2Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)TEXAS INSTRUMENTS INC·Filed 2004·Granted May 16, 2006·17 cites·22 claims
- 1368US7662688B2Application of different isolation schemes for logic and embedded memoryTEXAS INSTRUMENTS INC·Filed 2007·Granted Feb 16, 2010·2 cites·4 claims
- 1465US9245755B2Deep collector vertical bipolar transistor with enhanced gainTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 26, 2016·1 cites·13 claims
- 1565US6211769B1System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flowTEXAS INSTRUMENTS INC·Filed 1998·Granted Apr 3, 2001·20 cites·10 claims
- 1663US6333238B2Method for minimizing the temperature coefficient of resistance of passive resistors in an integrated circuit process flowTEXAS INSTRUMENTS INC·Filed 2000·Granted Dec 25, 2001·9 cites·10 claims
- 1761US7141468B2Application of different isolation schemes for logic and embedded memoryTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 28, 2006·6 cites·12 claims
- 1852US9379176B2Well resistors and polysilicon resistorsTEXAS INSTRUMENTS INC·Filed 2015·Granted Jun 28, 2016·0 cites·10 claims
- 1952US9177802B2High tilt angle plus twist drain extension implant for CHC lifetime improvementTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 3, 2015·0 cites·17 claims
- 2051US11455452B2Variable implant and wafer-level feed-forward for dopant dose optimizationTEXAS INSTRUMENTS INC·Filed 2020·Granted Sep 27, 2022·0 cites·25 claims
- 2150US9397164B2Deep collector vertical bipolar transistor with enhanced gainTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 19, 2016·0 cites·5 claims
- 2250US8753938B2Method for 1/F noise reduction in NMOS devicesTEXAS INSTRUMENTS INC·Filed 2014·Granted Jun 17, 2014·0 cites·8 claims
- 2349US2007166906A1Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of CarbonTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 2447US9431248B2High tilt angle plus twist drain extension implant for CHC lifetime improvementTEXAS INSTRUMENTS INC·Filed 2015·Granted Aug 30, 2016·0 cites·9 claims
- 2546US7199011B2Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbonTEXAS INSTRUMENTS INC·Filed 2003·Granted Apr 3, 2007·1 cites·19 claims
- 2640US8653607B2Method for 1/F noise reduction in NMOS devicesTSAO ALWIN JAMES·Filed 2012·Granted Feb 18, 2014·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →