Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of Carbon

Abstract

The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

1 - 35 . (canceled)  
   
   
       36 . A transistor comprising: 
 a gate structure formed over a substrate;    dopant implanted into the substrate adjacent the gate structure to form source, drain, source extension and drain extension regions; and    a channel underlying the gate structure, where some of the dopant may drift as a result of a heat treatment, 
 where the gate structure comprises: 
 a dielectric layer over the substrate;  
 a poly-SiGe layer with carbon over the dielectric layer; and  
 a poly-Si layer over the poly-SiGe layer.  
 
   
   
   
       37 . The transistor of  claim 36 , wherein the layer of poly-Si includes carbon.  
   
   
       38 . The transistor of  claim 37 , wherein the gate structure further comprises: 
 a polysilicon seed layer over the dielectric layer.    
   
   
       39 . The transistor of  claim 38 , wherein the seed layer includes carbon.  
   
   
       40 . The transistor of  claim 39 , wherein the gate structure is formed by an etching process, and wherein the poly-SiGe layer has a greater etch sensitivity to an etchant utilized in the process.  
   
   
       41 . The transistor of  claim 39 , wherein at least one of the seed layer, poly-SiGe layer and poly-Si layer contains a concentration of carbon between about 0.1 to 1.0 percent.  
   
   
       42 . The transistor of  claim 38 , wherein the seed layer has a thickness of about 100 Angstroms or less.  
   
   
       43 . The transistor of  claim 36 , wherein the poly-SiGe layer has a thickness of about 400 to 700 Angstroms.  
   
   
       44 . The transistor of  claim 36 , wherein the poly-Si, layer has a thickness of about 350 to 750 Angstroms.