Inventor · disambiguated record
Simon Shi-Ning Yang
Also filed as: YANG SIMON · YANG SIMON SHI-NING
40 granted patents·5 pending applications·1,252 citations·filing 1991–2024
98Inventor score
Files withYANGTZE MEMORY TECH CO LTD23INTEL CORP17CHARTERED SEMICONDUCTOR MFG2SEMICONDUCTOR MFG INT SHANGHAI2CHEN JOHN1
Top patents by PatentIndex Score
45 records- 0198US10283452B2Three-dimensional memory devices having a plurality of NAND stringsYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted May 7, 2019·61 cites·13 claims
- 0298US10147732B1Source structure of three-dimensional memory device and method for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Dec 4, 2018·66 cites·21 claims
- 0398US6521964B1Device having spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Feb 18, 2003·241 cites·6 claims
- 0498US6509618B2Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Jan 21, 2003·239 cites·8 claims
- 0598US6506652B2Method of recessing spacers to improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jan 14, 2003·239 cites·9 claims
- 0697US11758732B2Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2022·Granted Sep 12, 2023·3 cites·20 claims
- 0797US11527547B2Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2021·Granted Dec 13, 2022·3 cites·20 claims
- 0897US10923491B2Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2020·Granted Feb 16, 2021·4 cites·20 claims
- 0997US10593690B2Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Mar 17, 2020·21 cites·20 claims
- 1095US12170258B2Memory devices having vertical transistors and methods for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2021·Granted Dec 17, 2024·3 cites·18 claims
- 1194US11031333B2Three-dimensional memory devices having a plurality of NAND stringsYANGTZE MEMORY TECH CO LTD·Filed 2019·Granted Jun 8, 2021·8 cites·19 claims
- 1294US5780346AN2 O nitrided-oxide trench sidewalls and method of making isolation structureINTEL CORP·Filed 1996·Granted Jul 14, 1998·141 cites·30 claims
- 1393US10679721B2Structure and method for testing three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Jun 9, 2020·9 cites·15 claims
- 1492US11211397B2Three-dimensional memory devices and methods for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Dec 28, 2021·6 cites·14 claims
- 1588US10998079B2Structure and method for testing three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2020·Granted May 4, 2021·2 cites·17 claims
- 1688US7442637B2Method for processing IC designs for different metal BEOL processesCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Oct 28, 2008·21 cites·20 claims
- 1788US2025024683A1Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2024·Application pending·0 cites
- 1884US12137568B2Hybrid bonding contact structure of three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 1982US10804279B2Source structure of three-dimensional memory device and method for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Oct 13, 2020·4 cites·16 claims
- 2081US6593633B2Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Jul 15, 2003·16 cites·4 claims
- 2178US6777760B1Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Aug 17, 2004·13 cites·12 claims
- 2277US12142575B2Staircase etch control in forming three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2022·Granted Nov 12, 2024·0 cites·18 claims
- 2377US7381646B2Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al designCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jun 3, 2008·9 cites·29 claims
- 2475US10522474B2Staircase etch control in forming three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Dec 31, 2019·1 cites·19 claims
- 2575US2023422504A1Three-dimensional memory devices and methods for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2023·Application pending·0 cites
- 2673US11699657B2Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layerYANGTZE MEMORY TECH CO LTD·Filed 2021·Granted Jul 11, 2023·0 cites·17 claims
- 2771US9048300B2Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologiesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2012·Granted Jun 2, 2015·2 cites·17 claims
- 2871US6188117B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Feb 13, 2001·16 cites·28 claims
- 2970US11805646B2Three-dimensional memory devices and methods for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2020·Granted Oct 31, 2023·0 cites·21 claims
- 3069US5231053AProcess of forming a tri-layer titanium coating for an aluminum layer of a semiconductor deviceINTEL CORP·Filed 1991·Granted Jul 27, 1993·42 cites·7 claims
- 3168US6261925B1N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stressINTEL CORP·Filed 1998·Granted Jul 17, 2001·26 cites·16 claims
- 3266US10423176B2Low-dropout regulatorsYANGTZE MEMORY TECH CO LTD·Filed 2018·Granted Sep 24, 2019·1 cites·18 claims
- 3363US6740427B2Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making sameINTEL CORP·Filed 2001·Granted May 25, 2004·13 cites·25 claims
- 3462US11462474B2Three-dimensional memory devices having a plurality of NAND stringsYANGTZE MEMORY TECH CO LTD·Filed 2019·Granted Oct 4, 2022·0 cites·20 claims
- 3561US2020203285A1Staircase etch control in forming three-dimensional memory deviceYANGTZE MEMORY TECH CO LTD·Filed 2019·Application pending·0 cites
- 3655US6235598B1Method of using thick first spacers to improve salicide resistance on polysilicon gatesINTEL CORP·Filed 1998·Granted May 22, 2001·8 cites·10 claims
- 3754US5289035ATri-layer titanium coating for an aluminum layer of a semiconductor deviceINTEL CORP·Filed 1992·Granted Feb 22, 1994·21 cites·3 claims
- 3853US11264397B2Source structure of three-dimensional memory device and method for forming the sameYANGTZE MEMORY TECH CO LTD·Filed 2020·Granted Mar 1, 2022·0 cites·4 claims
- 3949US2012164803A1Strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologiesCHEN JOHN·Filed 2012·Application pending·0 cites
- 4047US7211872B2Device having recessed spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted May 1, 2007·1 cites·11 claims
- 4146US2007072376A1Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologiesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Application pending·0 cites
- 4238US6251762B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jun 26, 2001·5 cites·11 claims
- 4337US6271096B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Aug 7, 2001·2 cites·35 claims
- 4436US6566727B1N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stressINTEL CORP·Filed 1999·Granted May 20, 2003·4 cites·7 claims
- 4534US6268254B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jul 31, 2001·1 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →