Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

Abstract

A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.

1 . A method for forming a CMOS semiconductor integrated circuit device comprising: 
 providing a semiconductor substrate    forming a dielectric layer overlying the semiconductor substrate;    forming a gate layer overlying the dielectric layer;    patterning the gate layer to form a gate structure including edges;    forming a dielectric layer overlying the gate structure to protect the gate structure including the edges, the dielectric layer having a thickness of less than 1000 A nanometers;    patterning the dielectric layer overlying the gate structure;    etching a source region and a drain region adjacent to the gate structure using the patterned dielectric layer as a protective layer;    depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region; and    causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region.    
   
   
       2 . The method of  claim 1  wherein the dielectric layer is less than 300 Angstroms.  
   
   
       3 . The method of  claim 1  wherein the effective channel region has a length of a width of the gate structure.  
   
   
       4 . The method of  claim 1  wherein the semiconductor substrate is essential silicon material.  
   
   
       5 . The method of  claim 1  wherein the silicon germanium material is single crystalline.  
   
   
       6 . The method of  claim 1  wherein the silicon germanium has a ratio of silicon/germanium of 10% to 20%.  
   
   
       7 . The method of  claim 1  further comprising forming a spacer layer overlying the semiconductor substrate including silicon germanium, gate structure, and edges.  
   
   
       8 . The method of  claim 7  further comprising anisotropic etching the spacer layer to form sidewall spacers on edges of the gate layer.  
   
   
       9 . The method of  claim 1  wherein the depositing is provided using an epitaxial reactor.  
   
   
       10 . The method of  claim 1  wherein the compressive mode increases a mobility of holes in the channel region.  
   
   
       11 . A CMOS semiconductor integrated circuit device, the device comprising: 
 an NMOS device comprising a gate region, a source region, and a drain region;    an NMOS channel region formed between the source region and drain region;    a silicon carbide material formed within the source region and formed within the drain region;    whereupon the silicon carbide material causes the channel region to be in a tensile mode; and    a PMOS device comprising a gate region, a source region, and a drain region;    a PMOS channel region formed between the source region and the drain region;    a silicon germanium formed within the source region and formed with in the drain region; and    whereupon the silicon germanium material causes the channel region to be in a compressive mode.    
   
   
       12 . The device of  claim 11  wherein the semiconductor substrate is essentially silicon material.  
   
   
       13 . The device of  claim 11  wherein the NMOS channel region has a length of less than 90 nanometers.  
   
   
       14 . The device of  claim 11  wherein the PMOS channel region has a length of less than 90 nanometers.  
   
   
       15 . The device of  claim 11  wherein the silicon carbide material is single crystal material.  
   
   
       16 . The device of claim II wherein the silicon germanium material is single crystal material.  
   
   
       17 . The device of  claim 11  wherein the NMOS channel region has a length that. is substantially equal to a width of the gate region of the NMOS device.  
   
   
       18 . The device of  claim 17  wherein the length is exactly equal to the width of the gate region.  
   
   
       19 . The device of  claim 11  wherein the PMOS channel region has a length that is substantially equal as a width of the gate region of the PMOS device.  
   
   
       20 . The device of  claim 19  wherein the length is exactly equal to the width of the gate region.  
   
   
       21 . A method for forming a CMOS integrated circuit device, the method comprising: 
 providing a semiconductor substrate;    forming a gate layer overlying the semiconductor substrate;    patterning the gate layer to form an NMOS gate structure including edges and a PMOS gate structure including edges;    forming a dielectric layer overlying the NMOS gate structure to protect the NMOS gate structure including the edges and overlying the PMOS gate structure to protect the PMOS gate structure including the edges;    simultaneously etching a first source region and a first drain region adjacent to the NMOS gate structure and second source region and second drain region adjacent to the PMOS gate structure using the dielectric layer as a protective layer;    depositing silicon germanium material into the first source region and the first drain region to cause a channel region between the first source region and the first drain region of the NMOS gate structure to be strained in a compressive mode;    depositing silicon carbide material into the second source region and second drain region to cause the channel region between the second source region and the second drain region of the PMOS gate structure to be strained in a tensile mode.    
   
   
       22 . The method of  claim 21  wherein the tensile mode increases an electron mobility.  
   
   
       23 . The method of  claim 21  wherein the compressive mode increases a hole mobility.  
   
   
       24 . The method of  claim 21  wherein the channel region of the PMOS device has a length of 90 nanometers and less.  
   
   
       25 . The method of  claim 21  wherein the channel region of the NMOS device has a length of 90 nanometers and less.  
   
   
       26 . The method of  claim 21  wherein the silicon germanium material is an epitaxial material.  
   
   
       27 . The method of  claim 21  wherein the silicon carbide material is an epitaxial material.  
   
   
       28 . The method of  claim 21  wherein the silicon germanium material has a thickness ranging from about 200 Angstroms to 1000 Angstroms.  
   
   
       29 . The method of  claim 21  wherein the silicon carbide material has a thickness ranging from about 200 Angstroms to 1000 Angstroms.  
   
   
       30 . The method of  claim 21  further comprising forming sidewall spacers on the edges of the NMOS gate structure and the edges of the PMOS gate structure.  
   
   
       31 . The method of  claim 21  wherein the depositing the silicon germanium material is an in-situ doped process using a boron species, the boron species having a concentration ranging from about 10 19  to 10 20  atoms/cm 3 .  
   
   
       32 . The method of  claim 21  wherein the depositing the silicon carbide material is an in-situ doped process using a phosphorus species, the phosphorus species having a concentration ranging from about 10 19  to 10 20  atoms/cm 3 .  
   
   
       33 . The method of  claim 21  further comprising forming a refractory metal layer overlying the first source region and first drain region and the second source region and the second drain region.  
   
   
       34 . The method of  claim 21  wherein the first source region is an elevated first source region and the first drain region is an elevated first drain region; the second source region is an elevated second source region and the second drain region is an elevated second drain region.  
   
   
       35 . A PMOS integrated circuit device, the device comprising: 
 a semiconductor substrate comprising a surface region;    an isolation region formed within the semiconductor substrate;    a gate dielectric layer overlying the surface region of the semiconductor substrate;    a PMOS gate layer, the PMOS gate layer including a first edge and a second edge;    a first lightly doped region formed within a vicinity of the first edge;    a second lightly doped region formed within a vicinity of the second edge;    a first sidewall spacer formed on the first edge and on a portion of the first lightly doped region;    a second sidewall spacer formed on the second edge and on a portion of the second lightly doped region;    a first etched region of semiconductor substrate formed adjacent to the first sidewall spacer;    a second etched region of semiconductor substrate formed adjacent to the second sidewall spacer;    a first silicon germanium material formed within the first etched region to form a first source/drain region;    a second silicon germanium material formed within the second etched region to form a second source/drain region; and    a PMOS channel region formed between the first silicon germanium material and the second silicon germanium layer.    
   
   
       36 . The device of  claim 35  wherein the first silicon germanium material comprises a first surface that has a height above the surface region and the second silicon germanium material comprises a second surface that has a height above the surface region.