Inventor · disambiguated record
Youngtag Woo
Also filed as: WOO YOUNGTAG
24 granted patents·1 pending application·235 citations·filing 2004–2022
95Inventor score
Files withGLOBALFOUNDRIES INC18GLOBALFOUNDRIES US INC2GLOBALFOUNDIES INC1IBM1INTEGRATED DEVICE TECH1
Top patents by PatentIndex Score
25 records- 0197US12002869B2Gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Jun 4, 2024·4 cites·16 claims
- 0297US10236215B1Methods of forming gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·22 cites·19 claims
- 0397US9711511B1Vertical channel transistor-based semiconductor memory structureGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 18, 2017·30 cites·16 claims
- 0497US9406775B1Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraintsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 2, 2016·22 cites·15 claims
- 0596US9437481B2Self-aligned double patterning process for two dimensional patternsGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·15 cites·20 claims
- 0696US9324722B1Utilization of block-mask and cut-mask for forming metal routing in an IC deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 26, 2016·16 cites·20 claims
- 0795US9105510B2Double sidewall image transfer processGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 11, 2015·16 cites·17 claims
- 0895US8889561B2Double sidewall image transfer processWOO YOUNGTAG·Filed 2012·Granted Nov 18, 2014·44 cites·12 claims
- 0992US10770388B2Transistor with recessed cross couple for gate contact over active region integrationIBM·Filed 2018·Granted Sep 8, 2020·8 cites·9 claims
- 1092US10651284B2Methods of forming gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted May 12, 2020·7 cites·18 claims
- 1192US9627389B1Methods to form merged spacers for use in fin generation in IC devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 18, 2017·9 cites·20 claims
- 1291US9184169B2Methods of forming FinFET devices in different regions of an integrated circuit productGLOBALFOUNDIES INC·Filed 2014·Granted Nov 10, 2015·21 cites·24 claims
- 1387US9472464B1Methods to utilize merged spacers for use in fin generation in tapered IC devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 18, 2016·5 cites·20 claims
- 1481US10629701B1Self-aligned gate cut method and multilayer gate-cut pillar structureGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 21, 2020·2 cites·13 claims
- 1581US9406616B2Merged source/drain and gate contacts in SRAM bitcellGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 2, 2016·5 cites·21 claims
- 1674US10204861B2Structure with local contact for shorting a gate electrode to a source/drain regionGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 12, 2019·2 cites·16 claims
- 1772US9268897B2Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devicesYUAN LEI·Filed 2012·Granted Feb 23, 2016·3 cites·18 claims
- 1870US9466604B2Metal segments as landing pads and local interconnects in an IC deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·2 cites·20 claims
- 1966US10109636B2Active contact and gate contact interconnect for mitigating adjacent gate electrode shortagesGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·1 cites·8 claims
- 2065US11469309B2Gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES US INC·Filed 2020·Granted Oct 11, 2022·0 cites·10 claims
- 2163US10714591B2Gate structure for a transistor device with a novel pillar structure positioned thereaboveGLOBALFOUNDRIES INC·Filed 2020·Granted Jul 14, 2020·0 cites·16 claims
- 2256US10490455B2Gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 26, 2019·0 cites·13 claims
- 2348US7388262B2Nitrogen implementation to minimize device variationINTEGRATED DEVICE TECH·Filed 2004·Granted Jun 17, 2008·1 cites·10 claims
- 2444US8962483B2Interconnection designs using sidewall image transfer (SIT)GLOBALFOUNDRIES INC·Filed 2013·Granted Feb 24, 2015·0 cites·16 claims
- 2537US2017373071A1Vertical channel transistor-based semiconductor structureGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →