Inventor · disambiguated record
Thomas B. Berg
Also filed as: BERG THOMAS B · BERG THOMAS BENJAMIN
16 granted patents·6 pending applications·419 citations·filing 1988–2015
94Inventor score
Top patents by PatentIndex Score
22 records- 0192US7124410B2Distributed allocation of system hardware resources for multiprocessor systemsIBM·Filed 2002·Granted Oct 17, 2006·95 cites·18 claims
- 0286US6598120B1Assignment of building block collector agent to receive acknowledgments from other building block agentsIBM·Filed 2002·Granted Jul 22, 2003·47 cites·20 claims
- 0377US8230202B2Apparatus and method for condensing trace information in a multi-processor systemBERG THOMAS BENJAMIN·Filed 2008·Granted Jul 24, 2012·12 cites·26 claims
- 0477US6785779B2Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architectureINTERNAT BUSINESS MACHINES COM·Filed 2002·Granted Aug 31, 2004·27 cites·27 claims
- 0577US5003463AInterface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system busWANG LABORATORIES·Filed 1988·Granted Mar 26, 1991·70 cites·2 claims
- 0673US9141545B2Speculative read in a cache coherent microprocessorARM FINANCE OVERSEAS LTD·Filed 2014·Granted Sep 22, 2015·2 cites·13 claims
- 0768US6591370B1Multinode computer system with distributed clock synchronization systemIBM·Filed 1999·Granted Jul 8, 2003·50 cites·33 claims
- 0866US6795889B2Method and apparatus for multi-path data storage and retrievalIBM·Filed 2002·Granted Sep 21, 2004·17 cites·24 claims
- 0965US6973544B2Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent systemIBM·Filed 2002·Granted Dec 6, 2005·11 cites·9 claims
- 1065US5261057AI/O bus to system interfaceWANG LABORATORIES·Filed 1992·Granted Nov 9, 1993·52 cites·16 claims
- 1160US7093257B2Allocation of potentially needed resources prior to complete transaction receiptIBM·Filed 2002·Granted Aug 15, 2006·8 cites·32 claims
- 1258US6807586B2Increased computer peripheral throughput by using data available withholdingIBM·Filed 2002·Granted Oct 19, 2004·5 cites·14 claims
- 1356US8930634B2Speculative read in a cache coherent microprocessorARM FINANCE OVERSEAS LTD·Filed 2014·Granted Jan 6, 2015·0 cites·18 claims
- 1452US2009089510A1Speculative read in a cache coherent microprocessorMIPS TECH INC·Filed 2007·Application pending·0 cites
- 1551US2009249046A1Apparatus and method for low overhead correlation of multi-processor trace informationMIPS TECH INC·Filed 2008·Application pending·0 cites
- 1649US8001283B2Efficient, scalable and high performance mechanism for handling IO requestsMIPS TECH INC·Filed 2008·Granted Aug 16, 2011·0 cites·31 claims
- 1747US7552247B2Increased computer peripheral throughput by using data available withholdingIBM·Filed 2004·Granted Jun 23, 2009·0 cites·4 claims
- 1847US2009248988A1Mechanism for maintaining consistency of data written by io devicesMIPS TECH INC·Filed 2008·Application pending·0 cites
- 1945US2013067284A1Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace InformationBERG THOMAS BENJAMIN·Filed 2012·Application pending·0 cites
- 2043US5916314AMethod and apparatus for cache tag mirroringSEQUENT COMPUTER SYSTEMS INC·Filed 1996·Granted Jun 29, 1999·23 cites·24 claims
- 2140US2012290780A1Multithreaded Operation of A Microprocessor CacheKINTER RYAN C·Filed 2012·Application pending·0 cites
- 2237US2016117250A1Apparatus and Method of Throttling Hardware Pre-fetchIMAGINATION TECH LTD·Filed 2015·Application pending·0 cites
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