Speculative read in a cache coherent microprocessor

Abstract

A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.

1 . A microprocessor comprising:
 a plurality of processing cores; and   a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising:
 a request unit configured to receive a coherent request from a first one of the plurality of cores and to selectively issue a speculative request in response; 
 an intervention unit configured to send an intervention message associated with the coherent request to the plurality of cores; 
 a memory interface unit configured to receive the speculative request and to selectively forward the speculative request to a memory; and 
 a response unit configured to supply data associated with the coherent request to the first one of the plurality of cores. 
   
   
   
       2 . The microprocessor of  claim 1  wherein said memory interface unit comprises first, second and third tables 
   
   
       3 . The microprocessor of  claim 2  wherein an entry in said first table represents an index to said second table and wherein an entry in said second table represents an index to said third table. 
   
   
       4 . The microprocessor of  claim 3  wherein an index to said first table is allocated before a response to the intervention message is stored in the first table and before the speculative request is received by the memory interface unit. 
   
   
       5 . The microprocessor of  claim 4  wherein an index to said second table is allocated when the speculative request is stored in the memory interface unit. 
   
   
       6 . The microprocessor of  claim 5  wherein an index to said third table is allocated when the speculative request is issued to the memory. 
   
   
       7 . The microprocessor of  claim 3  wherein said request unit comprises:
 a fourth table storing a plurality of entries each associated with a different one of a plurality of pending coherent requests; and   a logic block configured to compare an address associated with the received coherent request to the plurality of addresses stored in the fourth table to determine if there is an address match, said logic block configured to issue the speculative request if an address match is not detected, said request unit further configured to assign an identifier to the received coherent request, said identifier representing the index to the first entry in the first table.   
   
   
       8 . The microprocessor of  claim 3  wherein said request unit comprises:
 a fourth table storing a plurality of entries each associated with a different one of a plurality of pending coherent requests; and   a logic block configured to issue the speculative request and to subsequently compare an address associated with the received coherent request to the plurality of addresses stored in the fourth table to determine if there is an address match, said logic block configured to cancel the speculative request if an address match is detected, said request unit further configured to assign an identifier to the received coherent request, said identifier representing the index to the first entry in the first table.   
   
   
       9 . The microprocessor of  claim 2  wherein said request unit is configured not to issue the speculative request unless a number of pending speculative requests not having intervention responses is less than a number of possible entries in the third table. 
   
   
       10 . A method of operating a microprocessor, said microprocessor comprising a plurality of processing cores and a cache coherence manager configured to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the method comprising:
 receiving a coherent request from a first one of the plurality of cores;   selectively issuing a speculative request in response to the received coherent request;   sending an intervention message associated with the coherent request to the plurality of cores; and   selectively forwarding the speculative request to a memory.   
   
   
       11 . The method of  claim 10  further comprising:
 defining an entry in a first table for use as an index to said second table; and   defining an entry in a second table for use as an index to a third table; said first, second and third tables being disposed in the cache coherence manager.   
   
   
       12 . The method of  claim 11  further comprising:
 allocating an index to said first table before a response to the intervention message is stored in the first table and before the speculative request is stored in a first queue.   
   
   
       13 . The method of  claim 12  further comprising:
 allocating an index to said second table when the speculative request is stored in a second queue.   
   
   
       14 . The method of  claim 13  further comprising:
 allocating an index to said third table when the speculative request is issued to the memory.   
   
   
       15 . The method of  claim 14  further comprising:
 comparing an address associated with the coherent request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests;   issuing the speculative request if an address match is not detected;   assigning an identifier to the issued speculative request; and   using said identifier as an index to the first entry stored in the first table.   
   
   
       16 . The method of  claim 14  further comprising:
 issuing the speculative request;   comparing an address associated with the issued speculative request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests;   canceling the speculative request if an address match is detected;   assigning an identifier to the issued speculative request; and   using said identifier as an index to the first entry stored in the first table.   
   
   
       17 . The method of  claim 14  further comprising:
 issuing the speculative request only if a number of pending speculative requests not having intervention responses is less than a number of possible entries in the third table.   
   
   
       18 . A computer readable storage medium including instructions defining logic blocks of a microprocessor comprising a plurality of processing cores and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the computer readable storage medium adapted for use by an electronic design automation application executed by a computer, wherein the logic blocks are configured to perform an operation comprising:
 receiving a coherent request from a first one of the plurality of cores;   selectively issuing a speculative request in response to the request received from the first one of the plurality of cores;   sending an intervention message associated with the coherent request to the plurality of cores; and   selectively forwarding the speculative request to a memory.   
   
   
       19 . The computer readable storage medium of  claim 18  wherein the logic blocks are configured to perform an operation comprising:
 defining an entry in a first table for use as an index to a second table; and   defining an entry in the second table for use as an index to a third table, said first, second and third tables being disposed in the cache coherence manager.   
   
   
       20 . The computer readable storage medium of  claim 19  wherein the logic blocks are configured to perform an operation comprising:
 allocating an index to said first table before a response to the intervention message is stored in the first table and before the speculative request is stored in a first queue;   allocating an index to said second table when the speculative request is stored in a second queue; and   allocating an index to said third table when the speculative request is issued to the memory.   
   
   
       21 . The computer readable storage medium of  claim 20  wherein the logic blocks are configured to perform an operation comprising:
 comparing an address associated with the coherent request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests;   issuing the speculative request if an address match is not detected;   assigning an identifier to the issued speculative request; and   using said identifier as an index to the first entry stored in the first table.   
   
   
       22 . The computer readable storage medium of  claim 20  wherein the logic blocks are configured to perform an operation comprising:
 issuing the speculative request;   comparing an address associated with the issued speculative request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests;   canceling the speculative request if an address match is detected;   assigning an identifier to the issued speculative request; and   using said identifier as an index to the first entry stored in the first table.   
   
   
       23 . A microprocessor comprising:
 a plurality of processing cores; and   a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising:   a plurality of configurable ports;   a plurality of configurable tables; and   a plurality of configurable queues.   
   
   
       24 . The microprocessor of  claim 23  wherein said cache coherence manager is further adapted to selectively issue a speculative request to a memory and to further issue an intervention message to the plurality of cores in response to a coherent request, wherein a first one of the plurality of configurable table stores a response to the intervention message using an index defined by an identifier allocated to the coherent request if the selectively issued speculative request is in a first one of the plurality of configurable queues when the response to the intervention message is received. 
   
   
       25 . The microprocessor of  claim 24  wherein an entry is allocated to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first one of the plurality of configurable queues to a second one of the plurality of configurable queues, wherein after the allocation of the entry in the second one of the plurality of configurable tables, the response to the intervention message is transferred to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables. 
   
   
       26 . The microprocessor of  claim 24  wherein an entry is allocated in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues, wherein the second one of the plurality of configurable tables stores the response to the intervention message if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received. 
   
   
       27 . The microprocessor of  claim 26  wherein an entry is allocated in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory, wherein the intervention message is copied from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables. 
   
   
       28 . A method of operating a microprocessor, said microprocessor comprising a plurality of processing cores and a cache coherence manager configured to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the method comprising:
 enabling one or more of a plurality of configurable ports disposed in the cache coherence manager to be selected for transferring information to and from the cache coherence manager;   enabling sizes of a plurality of configurable tables disposed in the cache coherence manager to be defined; and   enabling sizes of a plurality of configurable queues disposed in the cache coherence manager to be defined.   
   
   
       29 . The method of  claim 28  further comprising:
 selectively issuing a speculative request to a memory in response to a coherent request;   allocating an identifier to the coherent request;   issuing an intervention message to the plurality of cores in response to the coherent request;   storing a response to the intervention message in a first one of the plurality of configurable tables at an index defined by the identifier if the selectively issued speculative request is in a first one of the plurality of queues when the response to the intervention message is received.   
   
   
       30 . The method of  claim 29  further comprising:
 allocating an entry to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and   transferring the response to the intervention message to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables.   
   
   
       31 . The method of  claim 29  further comprising:
 allocating an entry in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and   storing the response to the intervention message in the second one of the plurality of configurable tables if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received.   
   
   
       32 . The method of  claim 31  further comprising:
 allocating an entry in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory; and   copying the intervention message from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables.   
   
   
       33 . A computer readable storage medium including instructions defining logic blocks of a microprocessor comprising a plurality of processing cores and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the computer readable storage medium adapted for use by an electronic design automation application executed by a computer, wherein the logic blocks are configured to perform an operation comprising:
 enabling one or more of a plurality of configurable ports disposed in the cache coherence manager to be selected for transferring information to and from the cache coherence manager;   enabling sizes of a plurality of configurable tables disposed in the cache coherence manager to be defined; and   enabling sizes of a plurality of configurable queues disposed in the cache coherence manager to be defined.   
   
   
       34 . The computer readable storage medium of  claim 33  wherein the logic blocks are configured to perform an operation comprising:
 selectively issuing a speculative request to a memory in response to a coherent request;   allocating an identifier to the coherent request;   issuing an intervention message to the plurality of cores in response to the coherent request;   storing a response to the intervention message in a first one of the plurality of configurable tables at an index defined by the identifier if the selectively issued speculative request is in a first one of the plurality of queues when the response to the intervention message is received.   
   
   
       35 . The computer readable storage medium of  claim 34  wherein the logic blocks are configured to perform an operation comprising:
 allocating an entry to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and   transferring the response to the intervention message to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables.   
   
   
       36 . The computer readable storage medium of  claim 34  wherein the logic blocks are configured to perform an operation comprising:
 allocating an entry in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and   storing the response to the intervention message in the second one of the plurality of configurable tables if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received.   
   
   
       37 . The method of  claim 36  further comprising:
 allocating an entry in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory; and   copying the intervention message from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables.