Inventor · disambiguated record
Tsu-Jae King Liu
Also filed as: LIU TSU-JAE · LIU TSU-JAE K · LIU TSU-JAE KING
13 granted patents·3 pending applications·753 citations·filing 2005–2017
92Inventor score
Top patents by PatentIndex Score
16 records- 0198US7605449B2Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation materialSYNOPSYS INC·Filed 2007·Granted Oct 20, 2009·336 cites·18 claims
- 0298US7508031B2Enhanced segmented channel MOS transistor with narrowed base regionsSYNOPSYS INC·Filed 2007·Granted Mar 24, 2009·343 cites·21 claims
- 0394US7807523B2Sequential selective epitaxial growthSYNOPSYS INC·Filed 2007·Granted Oct 5, 2010·34 cites·20 claims
- 0485US7560201B2Patterning a single integrated circuit layer using multiple masks and multiple masking layersSYNOPSYS INC·Filed 2008·Granted Jul 14, 2009·11 cites·15 claims
- 0581US8043943B2Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallizationUNIV CALIFORNIA·Filed 2009·Granted Oct 25, 2011·10 cites·37 claims
- 0680US7710771B2Method and apparatus for capacitorless double-gate storageUNIV CALIFORNIA·Filed 2007·Granted May 4, 2010·8 cites·9 claims
- 0777US10347501B2Enhanced patterning of integrated circuit layer by tilted ion implantationUNIV CALIFORNIA·Filed 2017·Granted Jul 9, 2019·2 cites·19 claims
- 0875US7995380B2Negative differential resistance pull up element for DRAMSYNOPSYS INC·Filed 2008·Granted Aug 9, 2011·5 cites·36 claims
- 0963US7494933B2Method for achieving uniform etch depth using ion implantation and a timed etchSYNOPSYS INC·Filed 2006·Granted Feb 24, 2009·1 cites·9 claims
- 1062US8686497B2DRAM cell utilizing a doubly gated vertical channelKWON WOOKHYUN·Filed 2012·Granted Apr 1, 2014·3 cites·9 claims
- 1152US9355860B2Method for achieving uniform etch depth using ion implantation and a timed etchLIU TSU-JAE KING·Filed 2009·Granted May 31, 2016·0 cites·10 claims
- 1251US2016268372A1Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed EtchSYNOPSYS INC·Filed 2016·Application pending·0 cites
- 1349US8592109B2Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layersSYNOPSYS INC·Filed 2013·Granted Nov 26, 2013·0 cites·13 claims
- 1445US8399183B2Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layersLIU TSU-JAE KING·Filed 2009·Granted Mar 19, 2013·0 cites·9 claims
- 1544US2006125017A1Stacked memory cell utilizing negative differential resistance devicesSYNOPSYS INC·Filed 2006·Application pending·0 cites
- 1638US2007120186A1Engineered barrier layer and gate gap for transistors with negative differential resistanceSYNOPSYS INC·Filed 2005·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →