Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch

Abstract

A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

1 . An integrated circuit comprising:
 a structure including a semiconductor material having a horizontal surface at least one vertical surface, the structure being subjected to a first ion implantation, thereby damaging the semiconductor material below the horizontal surface;   an isolation material contacting said at least one vertical surface of the semiconductor structure, the isolation material subjected to the first ion implantation while an upper surface of said isolation material is coplanar with said horizontal surface of said semiconductor structure, thereby damaging the isolation material, and then etched to a precise depth relative to said structure by simultaneously applying an etchant directly onto both said horizontal surface of said structure and the upper surface of said isolation material, whereby said precise depth is determined by a difference between an etch rate of said isolation material and an etch rate of said semiconductor material.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the isolation material is one of a dielectric, silicon dioxide and a field oxide. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the semiconductor material forms a transistor. 
     
     
         4 . The integrated circuit of  claim 1 , further comprising a second structure at least partially formed on said upper surface of said isolation material and disposed adjacent to said at least one vertical surface. 
     
     
         5 . The integrated circuit of  claim 4 , wherein said second structure comprises polycrystalline silicon. 
     
     
         6 . The integrated circuit of  claim 5 , further comprising a dielectric layer disposed between said at least one vertical surface of said structure and said second structure. 
     
     
         7 . The integrated circuit of  claim 5 , wherein said second structure comprises a capacitor. 
     
     
         8 . The integrated circuit of  claim 5 , further comprising a dielectric layer extending from said horizontal surface of said structure down said at least one vertical surface to said isolation material. 
     
     
         9 . The integrated circuit of  claim 1 , wherein the ion implantation includes argon. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the ion implantation includes germanium. 
     
     
         11 . The integrated circuit of  claim 1 , wherein the structure forms a fin-like channel region of a FinFET transistor, and said precise depth defines a fin height of said FinFET transistor. 
     
     
         12 . A method of fabricating FinFET transistors including fin-like channel regions comprising patterned semiconductor material, the method comprising:
 performing an ion implantation into an isolation material and said patterned semiconductor material, the isolation material being formed between ridges of the patterned semiconductor material, wherein performing the ion implantation comprises damaging the isolation material to a precise depth;   performing a timed etch to remove a damaged portion of the isolation material, thereby providing a vertical dimension of the isolation material in relation to the patterned semiconductor layer, which is unaffected by the timed etch, whereby the vertical dimension defines fin heights of said fin-like channel regions of said FinFET transistors; and   performing an annealing to repair the patterned semiconductor material,   wherein said damaged portion of the isolation material etches faster than underlying undamaged portions of said isolation material, thereby ensuring that the vertical dimension of the isolation material in relation to the patterned semiconductor material is substantially equal to the precise depth.   
     
     
         13 . The method of  claim 12 , wherein the isolation material comprises one of a dielectric, silicon dioxide and a field oxide. 
     
     
         14 . The method of  claim 12 , wherein the ion implantation includes argon. 
     
     
         15 . The method of  claim 12 , wherein the ion implantation includes germanium. 
     
     
         16 . A FinFET comprising:
 a fin-like channel region comprising a semiconductor structure having a horizontal surface and at least one vertical surface, the semiconductor structure being subjected to a first ion implantation, thereby damaging the semiconductor material below the horizontal surface;   an isolation material contacting said at least one vertical surface of the semiconductor structure, the isolation material subjected to the first ion implantation while an upper surface of said isolation material is coplanar with said horizontal surface of said semiconductor structure, thereby damaging the isolation material, and then etched to a precise depth relative to said semiconductor structure by simultaneously applying an etchant directly onto both said horizontal surface of said structure and the upper surface of said isolation material, whereby said precise depth is determined by a difference between an etch rate of said isolation material and an etch rate of said semiconductor structure and defines a fin height of said FinFET transistor.