Stacked memory cell utilizing negative differential resistance devices

Abstract

A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell.

1 . A memory cell comprising: 
 a first negative differential resistance field effect transistor (NDR-FET);    a second NDR-FET connected in series with the first NDR-FET; and    an access transistor connected between a data line and a junction between the first NDR-FET and the second NDR-FET,    wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.    
   
   
       2 . The memory cell of  claim 1 , wherein the access transistor is formed in a first semiconductor layer, 
 wherein the first NDR-FET and the second NDR-FET are formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and    wherein one of the first NDR-FET and the second NDR-FET overlies the access transistor.    
   
   
       3 . The memory cell of  claim 2 , wherein the first NDR-FET and the second NDR-FET share a common source/drain region.  
   
   
       4 . The memory cell of  claim 1 , wherein the first NDR-FET and the second NDR-FET are formed in a first semiconductor layer, 
 wherein the access transistor is formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and    wherein the access transistor overlies one of the first NDR-FET and the second NDR-FET.    
   
   
       5 . The memory cell of  claim 4 , wherein the first NDR-FET and the second NDR-FET share a common source/drain region.  
   
   
       6 . The memory cell of  claim 1 , wherein the first NDR-FET and the access transistor are formed in a first semiconductor layer, 
 wherein the second NDR-FET is formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and    wherein the second NDR-FET overlies one of the first NDR-FET and the access transistor.    
   
   
       7 . The memory cell of  claim 1 , wherein the first NDR-FET is formed in a first semiconductor layer, 
 wherein the second NDR-FET and the access transistor are formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and    wherein one of the second NDR-FET and the access transistor overlies the first NDR-FET.    
   
   
       8 . The memory cell of  claim 1 , wherein the first NDR-FET, the second NDR-FET, and the access transistor are arranged one above another.  
   
   
       9 . The memory cell of  claim 8 , wherein the first NDR-FET is formed in a first semiconductor layer, 
 wherein the second NDR-FET is formed in a second semiconductor layer,    wherein the access transistor is formed in a third semiconductor layer,    wherein the first semiconductor layer overlies the second semiconductor layer, and    wherein the second semiconductor layer overlies the third semiconductor layer.    
   
   
       10 . The memory cell of  claim 8 , wherein the first NDR-FET is formed in a first semiconductor layer, 
 wherein the second NDR-FET is formed in a second semiconductor layer,    wherein the access transistor is formed in a third semiconductor layer, and    wherein the third semiconductor layer overlies the first semiconductor layer and the second semiconductor layer overlies the third semiconductor layer.    
   
   
       11 . The memory cell of  claim 8 , wherein the first NDR-FET is formed in a first semiconductor layer, 
 wherein the second NDR-FET is formed in a second semiconductor layer,    wherein the access transistor is formed in a third semiconductor layer, and    wherein the third semiconductor layer overlies the first semiconductor layer and the second semiconductor layer.    
   
   
       12 . A method for making a memory cell, the method comprising: 
 forming a first negative differential resistance (NDR) field effect transistor (FET) in series with a second NDR-FET;    forming an access transistor for connecting a data line to a junction between the first NDR-FET and the second NDR-FET,    wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.    
   
   
       13 . The method of  claim 12 , wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, the method further comprising: 
 forming an insulating layer over the access transistor;    forming a second semiconductor layer over the insulating layer, wherein forming the first NDR-FET in series with the second NDR-FET comprises forming the first NDR-FET and the second NDR-FET in the second semiconductor layer such that one of the first NDR-FET and the second NDR-FET overlies the access transistor; and    forming a vertical interconnect between a source/drain region of the access transistor and the junction between the first NDR-FET and the second NDR-FET.    
   
   
       14 . The method of  claim 13 , wherein the junction between the first NDR-FET and the second NDR-FET comprises a shared source/drain region.  
   
   
       15 . The method of  claim 12 , wherein forming the forming the first NDR-FET in series with the second NDR-FET comprises forming the first NDR-FET and the second NDR-FET in a first semiconductor layer, the method further comprising: 
 creating an insulating layer over the first NDR-FET and the second NDR-FET;    creating a second semiconductor layer over the insulating layer, wherein forming the access transistor comprises forming the access transistor in the second semiconductor layer such that the access transistor overlies one of the first NDR-FET and the second NDR-FET; and    forming a vertical interconnect between a source/drain region of the access transistor and the junction between the first NDR-FET and the second NDR-FET.    
   
   
       16 . The method of  claim 15 , wherein the junction between the first NDR-FET and the second NDR-FET comprises a shared source/drain region.  
   
   
       17 . The method of  claim 12 , wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, and 
 wherein forming the first NDR-FET in series with the second NDR-FET comprises: 
 forming the first NDR-FET in the first semiconductor layer;  
 creating an insulating layer over the access transistor and the first NDR-FET;  
 creating a second semiconductor layer over the insulating layer; and  
 forming the second NDR-FET in the second semiconductor layer,  
 wherein the second NDR-FET overlies one of the first NDR-FET and the access transistor.  
   
   
   
       18 . The method of  claim 12 , wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, and 
 wherein forming the first NDR-FET in series with the second NDR-FET comprises: 
 creating a first insulating layer over the access transistor;  
 creating a second semiconductor layer over the first insulating layer;  
 forming the first NDR-FET in the second semiconductor layer such that the first NDR-FET overlies the access transistor;  
 creating a second insulating layer over the first NDR-FET;  
 creating a third semiconductor layer over the second insulating layer;  
 forming the second NDR-FET in the third semiconductor layer such that the second NDR-FET overlies the first NDR-FET; and  
 forming a vertical interconnect connecting a source/drain region of the second NDR-FET, a source/drain region of the first NDR-FET, and a source/drain region of the access transistor.  
   
   
   
       19 . The method of  claim 12 , wherein forming the first NDR-FET in series with the second NDR-FET comprises: 
 forming the first NDR-FET in a first semiconductor layer;    creating a first insulating layer over the first NDR-FET;    creating a second semiconductor layer over the first insulating layer;    forming the second NDR-FET in the second semiconductor layer such that the second NDR-FET overlies the first NDR-FET;    creating a second insulating layer over the second NDR-FET;    creating a third semiconductor layer over the second insulating layer, wherein forming the access transistor comprises forming the access transistor in the third semiconductor layer such that the access transistor overlies the second NDR-FET; and    forming a vertical interconnect connecting a source/drain region of the access transistor, a source/drain region of the second NDR-FET, and a source/drain region of the first NDR-FET.