Inventor · disambiguated record
Chin-Chiu Hsia
Also filed as: HSIA CHIN · HSIA CHIN CHIOU · HSIA CHIN-CHIU
19 granted patents·5 pending applications·309 citations·filing 1999–2015
94Inventor score
Top patents by PatentIndex Score
24 records- 0192US6737345B1Scheme to define laser fuse in dual damascene CU processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted May 18, 2004·79 cites·38 claims
- 0290US7592710B2Bond pad structure for wire bondingTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 22, 2009·19 cites·20 claims
- 0390US7253531B1Semiconductor bonding pad structureTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 7, 2007·23 cites·20 claims
- 0490US6361909B1Illumination aperture filter design using superpositionIND TECH RES INST·Filed 1999·Granted Mar 26, 2002·82 cites·20 claims
- 0578US8136070B2Shallow trench isolation dummy pattern and layout method using the sameDOONG KELVIN YIH-YUH·Filed 2010·Granted Mar 13, 2012·5 cites·13 claims
- 0673US7291557B2Method for forming an interconnection structure for ic metallizationTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 6, 2007·20 cites·16 claims
- 0771US6831365B1Method and pattern for reducing interconnect failuresTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 14, 2004·18 cites·17 claims
- 0871US6566752B2Bonding pad and method for manufacturing itIND TECH RES INST·Filed 2002·Granted May 20, 2003·16 cites·10 claims
- 0970US7042097B2Structure for reducing stress-induced voiding in an interconnect of integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted May 9, 2006·14 cites·20 claims
- 1070US6426555B1Bonding pad and method for manufacturing itIND TECH RES INST·Filed 2000·Granted Jul 30, 2002·15 cites·9 claims
- 1168US7849432B2Shallow trench isolation dummy pattern and layout method using the sameTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Dec 7, 2010·2 cites·20 claims
- 1255US7777338B2Seal ring structure for integrated circuit chipsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 17, 2010·6 cites·50 claims
- 1354US6835578B1Test structure for differentiating the line and via contribution in stress migrationTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 28, 2004·4 cites·32 claims
- 1453US7388263B2Shallow trench isolation dummy pattern and layout method using the sameTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 17, 2008·3 cites·8 claims
- 1551US9244161B2Ultrasound transmission circuit and time delay calibration method thereofIND TECH RES INST·Filed 2013·Granted Jan 26, 2016·1 cites·15 claims
- 1649US7312486B1Stripe board dummy metal for reducing coupling capacitanceTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 25, 2007·2 cites·16 claims
- 1745US7470994B2Bonding pad structure and method for making the sameTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 30, 2008·0 cites·11 claims
- 1844US2015036247A1Apparatus for a voltage protection tranceiver and device therewithIND TECH RES INST·Filed 2014·Application pending·0 cites
- 1943US2004079636A1Biomedical ion sensitive semiconductor sensor and sensor arrayFiled 2002·Application pending·0 cites
- 2043US2006055002A1Methods for enhancing die saw and packaging reliabilityTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 2140US7151052B2Multiple etch-stop layer deposition scheme and materialsTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 19, 2006·0 cites·7 claims
- 2240US2006108696A1Structure for reducing stress-induced voiding in an interconnect of integrated circuitsYAO CHIH-HSIANG·Filed 2006·Application pending·0 cites
- 2337US9973180B2Output stage circuitIND TECH RES INST·Filed 2015·Granted May 15, 2018·0 cites·12 claims
- 2437US2004251549A1Hybrid copper/low k dielectric interconnect integration method and deviceFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →