Inventor · disambiguated record
Vinay Chikarmane
Also filed as: CHIKARMANE VINAY · CHIKARMANE VINAY B
16 granted patents·11 pending applications·132 citations·filing 1997–2024
93Inventor score
Top patents by PatentIndex Score
27 records- 0195US7719062B2Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancementINTEL CORP·Filed 2006·Granted May 18, 2010·33 cites·21 claims
- 0293US11581419B2Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2020·Granted Feb 14, 2023·2 cites·21 claims
- 0392US11955534B2Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2022·Granted Apr 9, 2024·1 cites·20 claims
- 0492US8120119B2Stressed barrier plug slot contact structure for transistor performance enhancementFISCHER KEVIN J·Filed 2011·Granted Feb 21, 2012·16 cites·20 claims
- 0591US10777655B2Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2017·Granted Sep 15, 2020·3 cites·22 claims
- 0689US7968952B2Stressed barrier plug slot contact structure for transistor performance enhancementINTEL CORP·Filed 2006·Granted Jun 28, 2011·12 cites·10 claims
- 0786US10854731B2Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2019·Granted Dec 1, 2020·1 cites·20 claims
- 0885US8278718B2Stressed barrier plug slot contact structure for transistor performance enhancementFISCHER KEVIN J·Filed 2011·Granted Oct 2, 2012·6 cites·16 claims
- 0981US7070687B2Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturingINTEL CORP·Filed 2001·Granted Jul 4, 2006·26 cites·27 claims
- 1080US2025072078A1Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2024·Application pending·0 cites
- 1175US2024047556A1Heterogeneous metal line compositions for advanced integrated circuit structure fabricationINTEL CORP·Filed 2023·Application pending·0 cites
- 1267US7525197B2Barrier process/structure for transistor trench contact applicationsINTEL CORP·Filed 2006·Granted Apr 28, 2009·3 cites·9 claims
- 1363US7371311B2Modified electroplating solution components in a low-acid electrolyte solutionINTEL CORP·Filed 2003·Granted May 13, 2008·3 cites·7 claims
- 1460US7768126B2Barrier formation and structure to use in semiconductor devicesINTEL CORP·Filed 2006·Granted Aug 3, 2010·2 cites·6 claims
- 1557US7741219B2Method for manufacturing a semiconductor device using the self aligned contact (SAC) process flow for semiconductor devices with aluminum metal gatesINTEL CORP·Filed 2007·Granted Jun 22, 2010·1 cites·7 claims
- 1657US2006006071A1Method for improving electroplating in sub-0.1um interconnects by adjusting immersion conditionsCHE GUANGLI·Filed 2005·Application pending·0 cites
- 1756US7001641B2Seed layer treatmentINTEL CORP·Filed 2002·Granted Feb 21, 2006·4 cites·23 claims
- 1854US2005274619A1Modified electroplating solution components in a low-acid electrolyte solutionZIERATH DANIEL J·Filed 2005·Application pending·0 cites
- 1953US5804251ALow temperature aluminum alloy plug technologyINTEL CORP·Filed 1997·Granted Sep 8, 1998·19 cites·20 claims
- 2050US2009170309A1Barrier process/structure for transistor trench contact applicationsCHIKARMANE VINAY·Filed 2009·Application pending·0 cites
- 2147US2004245107A1Method for improving electroplating in sub-0.1um interconnects by adjusting immersion conditionsFiled 2003·Application pending·0 cites
- 2246US7582558B2Reducing corrosion in copper damascene processesINTEL CORP·Filed 2006·Granted Sep 1, 2009·0 cites·7 claims
- 2346US2006091018A1Methods for reducing protrusions and within die thickness variations on plated thin filmCAO YANG·Filed 2005·Application pending·0 cites
- 2443US2005112856A1Seed layer treatmentFiled 2004·Application pending·0 cites
- 2539US2004188265A1Methods for reducing protrusions and within die thickness variations on plated thin filmFiled 2003·Application pending·0 cites
- 2639US2008076246A1Through contact layer opening silicide and barrier layer formationPETERSON BRENNAN L·Filed 2006·Application pending·0 cites
- 2737US2005285269A1Substantially void free interconnect formationCAO YANG·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →