Seed layer treatment

Abstract

Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

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       24 . A die comprising: 
 a substrate; and    a patterned inter-layer dielectric on said substrate, the patterned inter-layer dielectric comprising a treated seed layer formed by exposure to heat in a reducing environment.    
   
   
       25 . The die of  claim 24  wherein the seed layer is one of copper, copper tin, copper indium, and copper aluminum.  
   
   
       26 . The die of  claim 24  further comprising a barrier below the seed layer and of one of a tantalum-based material and a titanium-based material.  
   
   
       27 . The die of  claim 24  wherein the die is of a wafer of a plurality of dice.  
   
   
       28 . A system comprising: 
 a package substrate; and    a die coupled to the package substrate and having a seed layer washed in a first solution with a first surfactant, the seed layer having a conductive material deposited thereon from a second solution with a second surfactant to form a circuit feature, the first surfactant and the second surfactant being non-competing surfactants.    
   
   
       29 . The system of  claim 28  wherein the circuit feature is at least one of a metal line and a filled via interconnect.  
   
   
       30 . The system of  claim 28  wherein the first surfactant and the second surfactant are the same surfactant.