Inventor · disambiguated record
Anthony Mowry
Also filed as: MOWRY ANTHONY · MOWRY ANTHONY C
23 granted patents·1 pending application·175 citations·filing 2007–2012
95Inventor score
Files withGLOBALFOUNDRIES INC11MOWRY ANTHONY6ADVANCED MICRO DEVICES INC2MOWRY ANTHONY C2STEPHAN ROLF2
Top patents by PatentIndex Score
24 records- 0194US7741663B2Air gap spacer formationGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 22, 2010·57 cites·20 claims
- 0290US8064197B2Heat management using power management informationMOWRY ANTHONY C·Filed 2009·Granted Nov 22, 2011·27 cites·21 claims
- 0388US7811876B2Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2008·Granted Oct 12, 2010·14 cites·19 claims
- 0486US8227266B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsMOWRY ANTHONY·Filed 2010·Granted Jul 24, 2012·6 cites·7 claims
- 0586US8212184B2Cold temperature control in a semiconductor deviceMOWRY ANTHONY·Filed 2009·Granted Jul 3, 2012·15 cites·25 claims
- 0685US8665592B2Heat management using power management informationMOWRY ANTHONY C·Filed 2011·Granted Mar 4, 2014·8 cites·16 claims
- 0783US7713763B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsADVANCED MICRO DEVICES INC·Filed 2008·Granted May 11, 2010·6 cites·11 claims
- 0881US8796807B2Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materialsSTEPHAN ROLF·Filed 2011·Granted Aug 5, 2014·8 cites·6 claims
- 0980US8093634B2In situ formed drain and source regions in a silicon/germanium containing transistor deviceMOWRY ANTHONY·Filed 2009·Granted Jan 10, 2012·9 cites·5 claims
- 1077US7939399B2Semiconductor device having a strained semiconductor alloy concentration profileGLOBALFOUNDRIES INC·Filed 2007·Granted May 10, 2011·7 cites·10 claims
- 1171US7879667B2Blocking pre-amorphization of a gate electrode of a transistorGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 1, 2011·3 cites·29 claims
- 1270US7790537B2Method for creating tensile strain by repeatedly applied stress memorization techniquesGLOBALFOUNDRIES INC·Filed 2007·Granted Sep 7, 2010·4 cites·11 claims
- 1366US7906385B2Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography stepsGLOBALFOUNDRIES INC·Filed 2008·Granted Mar 15, 2011·3 cites·6 claims
- 1466US7772077B2Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel regionADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 10, 2010·2 cites·9 claims
- 1563US7745337B2Method of optimizing sidewall spacer size for silicide proximity with in-situ cleanGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 29, 2010·2 cites·26 claims
- 1658US8564120B2Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backsideMOWRY ANTHONY·Filed 2009·Granted Oct 22, 2013·1 cites·20 claims
- 1757US8129236B2Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrodeGEHRING ANDREAS·Filed 2008·Granted Mar 6, 2012·1 cites·14 claims
- 1854US8530894B2Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regionsMOWRY ANTHONY·Filed 2012·Granted Sep 10, 2013·0 cites·7 claims
- 1954US8373244B2Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structureGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 12, 2013·2 cites·17 claims
- 2047US7977179B2Dopant profile tuning for MOS devices by adapting a spacer width prior to implantationGLOBALFOUNDRIES INC·Filed 2008·Granted Jul 12, 2011·0 cites·7 claims
- 2147US7923338B2Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequenceGLOBALFOUNDRIES INC·Filed 2008·Granted Apr 12, 2011·0 cites·24 claims
- 2246US8048330B2Method of forming an interlayer dielectric material having different removal rates during CMPGLOBALFOUNDRIES INC·Filed 2008·Granted Nov 1, 2011·0 cites·22 claims
- 2343US2009218601A1Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium materialSTEPHAN ROLF·Filed 2008·Application pending·0 cites
- 2442US8507351B2Dopant profile tuning for MOS devices by adapting a spacer width prior to implantationMOWRY ANTHONY·Filed 2011·Granted Aug 13, 2013·0 cites·17 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →