Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium material

Abstract

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

1 . A semiconductor device, comprising:
 a silicon-containing semiconductor layer;   a transistor formed in and above said silicon-containing semiconductor layer; and   a thermal sensing diode formed in said silicon-containing semiconductor layer, said thermal sensing diode comprising a P-doped region and an N-doped region, at least one of said P-doped region and said N-doped region comprising a germanium material.   
     
     
         2 . The semiconductor device of  claim 1 , wherein said at least one of said P-doped region and said N-doped region comprises a first silicon/germanium alloy material. 
     
     
         3 . The semiconductor device of  claim 2 , wherein said transistor comprises a gate electrode and drain and source regions and wherein a portion of said drain and source regions is comprised of a second silicon/germanium alloy material. 
     
     
         4 . The semiconductor device of  claim 3 , wherein said first and second silicon/germanium alloy materials have substantially the same germanium concentration. 
     
     
         5 . The semiconductor device of  claim 3 , further comprising a further transistor having drain and source regions formed in said silicon-containing semiconductor layer, wherein an amount of germanium of the drain and source regions of said further transistor is less than an amount of germanium of said transistor. 
     
     
         6 . The semiconductor device of  claim 5 , wherein said transistor is a P-channel transistor and said further transistor is an N-channel transistor. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a buried insulating layer located below said silicon-containing semiconductor layer. 
     
     
         8 . The semiconductor device of  claim 2 , wherein said first silicon/germanium alloy material is provided in a strained state. 
     
     
         9 . A semiconductor device, comprising:
 a silicon-containing semiconductor layer formed above a crystalline silicon-containing substrate;   a buried insulating layer located between said silicon-containing semiconductor layer and said substrate; and   a thermal sensing diode formed in said crystalline silicon-containing substrate, said thermal sensing diode comprising a P-doped region and an N-doped region, said P-doped region and said N-doped region comprising germanium.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising a first transistor formed in and above said silicon-containing semiconductor layer, said first transistor comprising a silicon/germanium alloy material in drain and source regions thereof. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the germanium in at least one of said P-doped and N-doped regions and said silicon/germanium alloy material are provided in a strained state. 
     
     
         12 . The semiconductor device of  claim 10 , further comprising a second transistor having drain and source regions, in which a germanium concentration is less than in the drain and source regions of said first transistor. 
     
     
         13 . The semiconductor device of  claim 12 , wherein said first and second transistors are of inverse conductivity type. 
     
     
         14 . The semiconductor device of  claim 10 , wherein said germanium material in at least one of said P-doped and N-doped regions is provided as a silicon/germanium alloy. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the silicon/germanium alloy in said at least one of said P-doped and N-doped regions and the silicon/germanium alloy material in said first transistor have substantially the same germanium concentration. 
     
     
         16 . The semiconductor device of  claim 15 , wherein said germanium concentration is approximately 15 atomic percent or more. 
     
     
         17 . A method, comprising:
 forming one or more recesses in a silicon-containing crystalline semiconductor material;   selectively growing a silicon/germanium alloy material in said one or more recesses;   forming at least one of a P-doped region and an N-doped region in said silicon/germanium alloy material, said at least one of said P-doped region and said N-doped region forming a PN junction of a diode structure; and   using a signal obtained from said diode structure for estimating a temperature of said diode structure.   
     
     
         18 . The method of  claim 17 , further comprising forming cavities next to a gate electrode of a transistor element and growing silicon/germanium in said cavities. 
     
     
         19 . The method of  claim 18 , wherein said silicon/germanium alloy material in said one or more recesses and said silicon/germanium in said cavities are grown in a common process. 
     
     
         20 . The method of  claim 18 , wherein said one or more recesses and said cavities are formed in a common etch process. 
     
     
         21 . The method of  claim 17 , wherein said silicon-containing crystalline semiconductor material is located below a buried insulating layer, above which is formed a device layer including a silicon-containing semiconductor material and isolation structures. 
     
     
         22 . The method of  claim 21 , further comprising forming an opening in said device layer and said buried insulating layer prior to forming said one or more recesses, said opening extending to said silicon-containing crystalline semiconductor material. 
     
     
         23 . The method of  claim 22 , further comprising forming a gate electrode above said device layer prior to forming said opening and forming cavities in said device layer next to said gate electrode and said one or more recesses in a common process.