Inventor · disambiguated record
Gyo-Young Jin
Also filed as: JIN GYO-YOUNG
26 granted patents·2 pending applications·451 citations·filing 1999–2013
96Inventor score
Files withSAMSUNG ELECTRONICS CO LTD21KIM JI YOUNG2CHOI JAY-BOK1KIM CHEON-BAE1SAMUNG ELECTRONICS CO LTD1
Top patents by PatentIndex Score
28 records- 0196US6683364B2Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Jan 27, 2004·118 cites·25 claims
- 0291US8884340B2Semiconductor devices including dual gate electrode structures and related methodsKIM JI-YOUNG·Filed 2011·Granted Nov 11, 2014·13 cites·19 claims
- 0391US7223649B2Method of fabricating transistor of DRAM semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted May 29, 2007·59 cites·61 claims
- 0490US7056781B2Method of forming fin field effect transistorSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jun 6, 2006·51 cites·26 claims
- 0586US6642125B2Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming sameSAMSUNG ELECTRONICS CO LTD·Filed 2001·Granted Nov 4, 2003·37 cites·22 claims
- 0685US7015106B2Double gate field effect transistor and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Mar 21, 2006·35 cites·13 claims
- 0784US7622778B2Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a voidSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Nov 24, 2009·13 cites·15 claims
- 0883US9276074B2Methods of fabricating semiconductor devices having buried channel arrayCHOI JAY-BOK·Filed 2013·Granted Mar 1, 2016·8 cites·12 claims
- 0981US8264022B2Semiconductor device including contact plug and associated methodsYOON JAE-MAN·Filed 2009·Granted Sep 11, 2012·10 cites·11 claims
- 1079US9349724B2Semiconductor device having capacitorsSAMSUNG ELECTRONICS CO LTD·Filed 2012·Granted May 24, 2016·6 cites·19 claims
- 1178US7288823B2Double gate field effect transistor and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Oct 30, 2007·7 cites·7 claims
- 1277US8492832B2Semiconductor deviceKIM JI-YOUNG·Filed 2012·Granted Jul 23, 2013·4 cites·16 claims
- 1377US8362536B2Semiconductor device having vertical channel transistor and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2010·Granted Jan 29, 2013·4 cites·30 claims
- 1476US6194309B1Method for forming contactSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Feb 27, 2001·48 cites·13 claims
- 1575US7501668B2Semiconductor memory devices having contact pads with silicide caps thereonSAMUNG ELECTRONICS CO LTD·Filed 2006·Granted Mar 10, 2009·5 cites·17 claims
- 1674US8785998B2Semiconductor device having vertical channel transistor and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2012·Granted Jul 22, 2014·3 cites·22 claims
- 1766US7737512B2Integrated circuit devices having uniform silicide junctionsSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jun 15, 2010·2 cites·38 claims
- 1859US7329927B2Integrated circuit devices having uniform silicide junctionsSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Feb 12, 2008·1 cites·22 claims
- 1959US7265011B2Method of manufacturing a transistorSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Sep 4, 2007·6 cites·51 claims
- 2057US7307008B2Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact holeSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Dec 11, 2007·7 cites·22 claims
- 2156US6974752B2Methods of fabricating integrated circuit devices having uniform silicide junctionsSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Dec 13, 2005·5 cites·27 claims
- 2255US6875649B2Methods for manufacturing integrated circuit devices including an isolation region defining an active region areaSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Apr 5, 2005·5 cites·17 claims
- 2352US7144798B2Semiconductor memory devices having extending contact pads and related methodsSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Dec 5, 2006·4 cites·58 claims
- 2449US7833864B2Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrateSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Nov 16, 2010·0 cites·23 claims
- 2547US7465988B2Semiconductor device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Dec 16, 2008·0 cites·7 claims
- 2646US7297596B2Method of manufacturing a semiconductor device having a switching functionSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Nov 20, 2007·0 cites·13 claims
- 2740US2004021197A1Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetweenFiled 2003·Application pending·0 cites
- 2837US2013140265A1Methods of forming pattern structures and methods of forming capacitors using the sameKIM CHEON-BAE·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →