Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween

Abstract

An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

What is claimed:  
     
         1 . An integrated circuit comprising: 
 an integrated circuit substrate;    first and second adjacent p-type doped regions spaced-apart from one another in the integrated circuit substrate;    a trench in the integrated circuit substrate between the first and second adjacent p-type doped regions; and    an insulator layer in the trench having a side wall, wherein the side wall is free of a layer thereon that reduces a stress between the integrated circuit substrate and the insulator layer.    
     
     
         2 . An integrated circuit according to  claim 1  further comprising: 
 a dielectric material in the trench directly on the side wall.  
 
     
     
         3 . An integrated circuit according  claim 1  wherein the trench comprises a first trench and the side wall comprises a first side wall and the insulator layer comprises a first insulator layer, the integrated circuit further comprising: 
 first and second adjacent n-type doped regions spaced-apart from one another in the integrated circuit substrate;  
 a second trench in the integrated circuit substrate between the first and second adjacent n-type doped regions;  
 a second insulator layer in the second trench having a second side wall; and  
 a liner layer on the second side wall that reduces a stress between the integrated circuit substrate and the second insulator layer.  
 
     
     
         4 . An integrated circuit according to  claim 3  wherein the dielectric material comprises a first dielectric material, the integrated circuit further comprising: 
 a second dielectric material in the second trench on the liner layer.  
 
     
     
         5 . An integrated circuit according to  claim 1  wherein the side wall is free of silicon nitride.  
     
     
         6 . An integrated circuit according to  claim 3  further comprising: 
 a core region of the integrated circuit substrate;  
 a peripheral region of the integrated circuit substrate; and  
 a cell region of the integrated circuit substrate that is spaced apart from the core and peripheral regions and having a greater density of integrated circuit devices therein than the core and peripheral regions, wherein the first trench is in one of the peripheral and core regions and wherein the second trench is in the cell region.  
 
     
     
         7 . An integrated circuit according to  claim 1  further comprising: 
 a core region of the integrated circuit substrate;  
 a peripheral region of the integrated circuit substrate; and  
 a cell region of the integrated circuit substrate that is spaced apart from the core and peripheral regions and having a greater density of integrated circuit devices therein than the core and peripheral regions, wherein the trench is between the core and peripheral regions and the cell region.  
 
     
     
         8 . An integrated circuit according to  claim 1  further comprising: 
 a core region of the integrated circuit substrate;  
 a peripheral region of the integrated circuit substrate; and  
 a cell region of the integrated circuit substrate that is spaced apart from the core and peripheral regions and having a greater density of integrated circuit devices therein than the core and peripheral regions, wherein the trench is in one of the core and peripheral regions.  
 
     
     
         9 . An integrated circuit comprising: 
 an integrated circuit substrate;    a core region of the integrated circuit substrate;    a peripheral region of the integrated circuit substrate;    a cell region of the integrated circuit substrate that is spaced apart from the core and peripheral regions and having a greater density of integrated circuit devices therein than the core and peripheral regions;    a first trench in one of the peripheral and core regions of integrated circuit substrate;    a first insulator layer in the first trench having a first side wall, wherein the first side wall is free of a layer that reduces a stress between the integrated circuit substrate and the first insulator layer;    a second trench in cell region of the integrated circuit substrate;    a second insulator layer in the second trench having a second side wall; and    a liner layer on the second side wall that reduces a stress between the integrated circuit substrate and the second insulator layer.    
     
     
         10 . An integrated circuit according to  claim 9  wherein the first trench is located between first and second adjacent p-type doped regions and wherein the second trench is located between first and second adjacent n-type doped regions.  
     
     
         11 . An integrated circuit according to  claim 9  further comprising: 
 a first dielectric material in the first trench directly on the first side wall; and  
 a liner layer on the second side wall that reduces a stress between the integrated circuit substrate and the second insulator layer; and  
 a second dielectric material directly on the liner layer.  
 
     
     
         12 . A semiconductor device having a shallow trench isolation (STI) structure, comprising: 
 a semiconductor substrate having a plurality of trenches therein that provide isolation between a cell region of the semiconductor substrate that includes memory devices therein and core and peripheral regions of the semiconductor substrate including a PMOS transistor;    a side wall oxide layer on inner surfaces of the plurality of trenches;    a relief liner on the side wall oxide layer of at least one trench in the cell region; and    a dielectric material in the plurality of trenches.    
     
     
         13 . A semiconductor device according to  claim 12  wherein the side wall oxide layer has a thickness of about 20 to 240 Å.  
     
     
         14 . A semiconductor device according to  claim 12  wherein the relief liner comprises a silicon nitride layer or a silicon oxynitride layer.  
     
     
         15 . A semiconductor device according to  claim 12  wherein the dielectric material comprises a high density plasma dielectric layer.  
     
     
         16 . An integrated circuit comprising: 
 a liner layer on side walls of first isolation trenches located in a cell region of an integrated circuit substrate to provide stress relief between a dielectric in the first isolation trenches and the substrate; and    second isolation trenches located in a peripheral region of the substrate having side walls that are free of the liner layer.    
     
     
         17 . An integrated circuit according to  claim 16  wherein the first isolation trenches are narrower than the second isolation trenches.  
     
     
         18 . An integrated circuit according to  claim 16  wherein the first isolation trenches have a depth in a range between about 0.1 μm and  1.5 μm.    
     
     
         19 . An integrated circuit according to  claim 16  wherein the liner layer comprises one of a silicon nitride layer and a oxynitride layer having a thickness in a range between about 50 Å and about 100 Å.