Inventor · disambiguated record
Randall Cher Liang Cha
Also filed as: CHA RANDALL · CHA RANDALL C L · CHA RANDALL CHER LIANG
35 granted patents·3 pending applications·807 citations·filing 2000–2022
98Inventor score
Files withCHARTERED SEMICONDUCTOR MFG31CHESTNUT SPRINGS LLC3CHARTERED SEMICONDUCTOR MANFAC1CHARTERED SEMICONDUCTORS MAUFA1LIM YEOW KHENG1
Top patents by PatentIndex Score
38 records- 0196US6348385B1Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constantCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 19, 2002·128 cites·12 claims
- 0293US10752840B2Flame retardant compositions and processes for preparation thereofCHESTNUT SPRINGS LLC·Filed 2017·Granted Aug 25, 2020·24 cites·17 claims
- 0393US6632712B1Method of fabricating variable length vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 14, 2003·89 cites·31 claims
- 0492US11608472B2Method for imparting flame retardancy to a substrate materialCHESTNUT SPRINGS LLC·Filed 2022·Granted Mar 21, 2023·3 cites·17 claims
- 0591US11326104B2Process for preparing flame retardant compositionsCHESTNUT SPRINGS LLC·Filed 2020·Granted May 10, 2022·3 cites·18 claims
- 0690US6468851B1Method of fabricating CMOS device with dual gate electrodeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 22, 2002·55 cites·39 claims
- 0789US6319767B1Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 20, 2001·50 cites·29 claims
- 0887US6387747B1Method to fabricate RF inductors with minimum areaCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·57 cites·29 claims
- 0986US6355563B1Versatile copper-wiring layout design with low-k dielectric integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Mar 12, 2002·46 cites·33 claims
- 1083US6558994B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTORS MAUFA·Filed 2001·Granted May 6, 2003·36 cites·13 claims
- 1181US6284590B1Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitorsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·29 cites·27 claims
- 1279US6613652B2Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performanceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 2, 2003·28 cites·33 claims
- 1378US6534390B1Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structureCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 18, 2003·21 cites·26 claims
- 1476US6531386B1Method to fabricate dish-free copper interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 11, 2003·23 cites·45 claims
- 1575US6387784B1Method to reduce polysilicon depletion in MOS transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·22 cites·25 claims
- 1675US6319772B1Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 20, 2001·14 cites·35 claims
- 1773US6664153B2Method to fabricate a single gate with dual work-functionsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 16, 2003·18 cites·22 claims
- 1873US6429109B1Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gateCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 6, 2002·18 cites·35 claims
- 1973US6376360B1Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacersCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 23, 2002·20 cites·22 claims
- 2072US6841441B2Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jan 11, 2005·12 cites·37 claims
- 2171US6284610B1Method to reduce compressive stress in the silicon substrate during silicidationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·19 cites·31 claims
- 2270US6432797B1Simplified method to reduce or eliminate STI oxide divotsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 13, 2002·13 cites·31 claims
- 2367US6384437B1Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 7, 2002·9 cites·6 claims
- 2466US6468880B1Method for fabricating complementary silicon on insulator devices using wafer bondingCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·14 cites·14 claims
- 2565US6780691B2Method to fabricate elevated source/drain transistor with large area for silicidationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 24, 2004·12 cites·37 claims
- 2662US6610604B1Method of forming small transistor gates by using self-aligned reverse spacer as a hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·10 cites·30 claims
- 2760US7119010B2Integrated circuit with self-aligned line and via and manufacturing method thereforCHARTERED SEMICONDUCTOR MANFAC·Filed 2002·Granted Oct 10, 2006·10 cites·9 claims
- 2857US6849928B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 1, 2005·6 cites·10 claims
- 2956US8766454B2Integrated circuit with self-aligned line and viaLIM YEOW KHENG·Filed 2006·Granted Jul 1, 2014·1 cites·10 claims
- 3054US6544848B1Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacersCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 8, 2003·6 cites·25 claims
- 3151US6399471B1Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron applicationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 4, 2002·4 cites·7 claims
- 3247US6828082B2Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 7, 2004·1 cites·51 claims
- 3347US6727151B2Method to fabricate elevated source/drain structures in MOS transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Apr 27, 2004·3 cites·32 claims
- 3445US6878623B2Technique to achieve thick silicide film for ultra-shallow junctionsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 12, 2005·3 cites·25 claims
- 3543US2005089777A1Method to pattern small features by using a re-flowable hard maskCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3643US2005101083A1Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3739US6472697B2Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron applicationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 29, 2002·0 cites·5 claims
- 3830US2002102802A1Novel technique to achieve thick silicide film for ultra-shallow junctionsFiled 2001·Application pending·0 cites
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