Inventor · disambiguated record
Tom Hameenanttila
Also filed as: HAMEENANTTILA TOM · HAMEENANTTILA TOM M · HAMEENANTTILA TOM MARKO
21 granted patents·1 pending application·443 citations·filing 1999–2018
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
22 records- 0197US9223709B1Thread-aware cache memory managementMARVELL INT LTD·Filed 2013·Granted Dec 29, 2015·49 cites·21 claims
- 0296US8918625B1Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparisonO'BLENESS R FRANK·Filed 2011·Granted Dec 23, 2014·59 cites·19 claims
- 0395US9026769B1Detecting and reissuing of loop instructions in reorder structureJAMIL SUJAT·Filed 2012·Granted May 5, 2015·43 cites·20 claims
- 0495US8990505B1Cache memory bank selectionJAMIL SUJAT·Filed 2008·Granted Mar 24, 2015·58 cites·34 claims
- 0592US9058272B1Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addressesMARVELL INT LTD·Filed 2013·Granted Jun 16, 2015·26 cites·17 claims
- 0690US8943273B1Method and apparatus for improving cache efficiencyJAMIL SUJAT·Filed 2009·Granted Jan 27, 2015·31 cites·20 claims
- 0788US8458404B1Programmable cache access protocol to optimize power consumption and performanceDELGROSS JOSEPH·Filed 2009·Granted Jun 4, 2013·24 cites·20 claims
- 0887US8135916B1Method and apparatus for hardware-configurable multi-policy coherence protocolO'BLENESS R FRANK·Filed 2009·Granted Mar 13, 2012·19 cites·11 claims
- 0986US9606800B1Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architectureMARVELL INT LTD·Filed 2013·Granted Mar 28, 2017·9 cites·20 claims
- 1083US8806181B1Dynamic pipeline reconfiguration including changing a number of stagesO'BLENESS R FRANK·Filed 2009·Granted Aug 12, 2014·14 cites·12 claims
- 1181US9442735B1Method and apparatus for processing speculative, out-of-order memory access instructionsMARVELL INT LTD·Filed 2013·Granted Sep 13, 2016·6 cites·20 claims
- 1281US8631206B1Way-selecting translation lookaside bufferO'BLENESS R FRANK·Filed 2008·Granted Jan 14, 2014·11 cites·11 claims
- 1379US6611856B1Processing multiply-accumulate operations in a single cycleINTEL CORP·Filed 1999·Granted Aug 26, 2003·75 cites·15 claims
- 1477US8296525B1Method and apparatus for data-less bus queryO'BLENESS FRANK·Filed 2009·Granted Oct 23, 2012·9 cites·20 claims
- 1576US9195524B1Hardware support for performance analysisWIESNER ROBERT·Filed 2011·Granted Nov 24, 2015·5 cites·18 claims
- 1672US8688919B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2012·Granted Apr 1, 2014·2 cites·20 claims
- 1770US9619402B1Method and apparatus for optimizing translation of a virtual memory address into a physical memory address in a processor having virtual memoryMARVELL INT LTD·Filed 2013·Granted Apr 11, 2017·3 cites·15 claims
- 1856US9086976B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2014·Granted Jul 21, 2015·0 cites·20 claims
- 1955US8769204B1Programmable cache access protocol to optimize power consumption and performanceMARVELL INT LTD·Filed 2013·Granted Jul 1, 2014·0 cites·20 claims
- 2050US9892051B1Method and apparatus for use of a preload instruction to improve efficiency of cacheMARVELL INT LTD·Filed 2015·Granted Feb 13, 2018·0 cites·23 claims
- 2144US2003172101A1Processing multiply-accumulate operations in a single cycleFiled 2003·Application pending·0 cites
- 2239US11301253B2Branch prediction structure indexed based on return address popped from a call-return stackADVANCED RISC MACH LTD·Filed 2018·Granted Apr 12, 2022·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →